| 31 Jul 2023 |
 jfng | the relationship isn't fully symmetrical, for sure | 18:39:56 |
| jfng | e.g. bus writes happen on the entire register, but peripherals can do them at the bit granularity if needed | 18:40:47 |
 galibert | even then, "full register" can be say 16 bits and a write be only on 8 | 18:41:27 |
| galibert | from the host side | 18:41:33 |
| jfng | no | 18:41:34 |
| galibert | no? | 18:41:53 |
| jfng | the multiplexer will only commit writes if all 16 bits are written | 18:42:02 |
| galibert | you ignore lane enables or you segfault on access? | 18:42:05 |
| galibert | ah, you drop writes. Interesting | 18:42:22 |
| jfng | if you only write the first 8 bits, then the transaction is ignored | 18:42:22 |
| jfng | from the RegisterInterface point of view, bus writes are done atomically to the full register | 18:43:04 |
| galibert | You realize you just thrown all the "we want to reproduce existing interfaces" arguments out? | 18:43:17 |
| galibert | * You realize you've just thrown all the "we want to reproduce existing interfaces" arguments out? | 18:43:27 |
| galibert | because logically partial writes are commonly accepted | 18:43:52 |
 vegard_e | not really | 18:44:04 |
| vegard_e | it's rather common for peripheral buses to not have byte lanes, which can give pretty surprising results if you attempt a byte write | 18:44:36 |
| vegard_e | I've experienced at least some platforms where a byte write to a peripheral register ends up with the byte replicated and written into every byte of the register | 18:45:49 |
| jfng | ouch | 18:46:10 |
| vegard_e | i.e. a byte write of 0x54 to the second byte lane is effectively a write of 0x54545454 & 0x0000ff00, and dropping the byte lanes drops the second half of that | 18:48:06 |
| galibert | Sounds very 680x0 | 18:48:24 |
| galibert | (we have to emulat byte smearing in mame because of that kind of issues) | 18:48:45 |
| galibert | * (we have to emulate byte smearing in mame because of that kind of issues) | 18:48:52 |
| vegard_e | this is still what modern microcontrollers do | 18:49:09 |
| jfng | also, if some design really wants partial writes (instead of say, RMWs), then i guess it could simply implement its own csr.Multiplexer variant | 18:50:10 |
 cr1901 | it's how litex does it as well; wishbone provides SEL lines to determine which writes/reads actually get through | 18:50:37 |
| galibert | jfng: personally I don't really care, it's just that Catherine seemed to consider replicating existing interfaces important. If that aspect isn't that important, all good | 18:51:14 |
|  brady.se joined the room. | 18:51:57 |
| brady.se changed their display name from brady.se to brady.se#0. | 18:51:58 |
| brady.se changed their display name from brady.se#0 to brady.se. | 18:51:59 |
| galibert | (for emulation I don't use wishbone in the first place for extremely obvious reasons) | 18:52:08 |
