Amaranth HDL

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Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org7 Servers

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31 Jul 2023
@jfng:matrix.orgjfngthe relationship isn't fully symmetrical, for sure18:39:56
@jfng:matrix.orgjfnge.g. bus writes happen on the entire register, but peripherals can do them at the bit granularity if needed18:40:47
@galibert:matrix.orggaliberteven then, "full register" can be say 16 bits and a write be only on 818:41:27
@galibert:matrix.orggalibertfrom the host side18:41:33
@jfng:matrix.orgjfngthe multiplexer will only commit writes if all 16 bits are written18:42:02
@galibert:matrix.orggalibertyou ignore lane enables or you segfault on access?18:42:05
@galibert:matrix.orggalibertah, you drop writes. Interesting18:42:22
@jfng:matrix.orgjfngif you only write the first 8 bits, then the transaction is ignored18:42:22
@jfng:matrix.orgjfng from the RegisterInterface point of view, bus writes are done atomically to the full register 18:43:04
@galibert:matrix.orggalibertYou realize you just thrown all the "we want to reproduce existing interfaces" arguments out?18:43:17
@galibert:matrix.orggalibert * You realize you've just thrown all the "we want to reproduce existing interfaces" arguments out?18:43:27
@galibert:matrix.orggalibertbecause logically partial writes are commonly accepted18:43:52
@_discord_157944445168254976:catircservices.orgvegard_e not really 18:44:04
@_discord_157944445168254976:catircservices.orgvegard_e it's rather common for peripheral buses to not have byte lanes, which can give pretty surprising results if you attempt a byte write 18:44:36
@_discord_157944445168254976:catircservices.orgvegard_e I've experienced at least some platforms where a byte write to a peripheral register ends up with the byte replicated and written into every byte of the register 18:45:49
@_discord_157944445168254976:catircservices.orgvegard_e i.e. a byte write of 0x54 to the second byte lane is effectively a write of 0x54545454 & 0x0000ff00, and dropping the byte lanes drops the second half of that 18:48:06
@galibert:matrix.orggalibertSounds very 680x018:48:24
@galibert:matrix.orggalibert(we have to emulat byte smearing in mame because of that kind of issues)18:48:45
@galibert:matrix.orggalibert * (we have to emulate byte smearing in mame because of that kind of issues)18:48:52
@_discord_157944445168254976:catircservices.orgvegard_e this is still what modern microcontrollers do 18:49:09
@jfng:matrix.orgjfng also, if some design really wants partial writes (instead of say, RMWs), then i guess it could simply implement its own csr.Multiplexer variant 18:50:10
@libera_cr1901:catircservices.orgcr1901 it's how litex does it as well; wishbone provides SEL lines to determine which writes/reads actually get through 18:50:37
@galibert:matrix.orggalibert jfng: personally I don't really care, it's just that Catherine seemed to consider replicating existing interfaces important. If that aspect isn't that important, all good 18:51:14
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@galibert:matrix.orggalibert(for emulation I don't use wishbone in the first place for extremely obvious reasons)18:52:08

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