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stm32-rs

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2 Feb 2023
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})(with an external PHY)20:29:46
@dirbaio:matrix.orgdirbaiointentionally cut-down to save silicon costs I guess20:29:47
@dirbaio:matrix.orgdirbaioand anyway20:29:58
@dirbaio:matrix.orgdirbaiothe distinction between "OTG FS" and "OTG HS but with only a FS PHY" is irrelevant20:30:13
@dirbaio:matrix.orgdirbaiothe registers and the driver for both are the same20:30:23
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})yeah sorry if I'm derailing too much, I'm just trying to understand20:30:27
@dirbaio:matrix.orgdirbaiojust the HS one has a few more bits to enable HS stuff20:30:38
@dirbaio:matrix.orgdirbaioso in practice it doesn't matter, all you care is "it can't do HS"20:31:20
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})sure20:31:29
@dirbaio:matrix.orgdirbaiohence why I was arguing the OTG_HS1 / OTG_HS2 naming is wrong20:31:33
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})
In reply to @dngrs:matrix.org
and/or "you could use it at HS speed if it had ULPI pins for that peripheral"?
is this interpretation correct though?
20:31:38
@dirbaio:matrix.orgdirbaiono idea!20:31:55
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})ha, ok20:31:59
@dirbaio:matrix.orgdirbaiomaybe? or maybe it's had that stuff optimized out of the silicon20:32:26
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})yeah I guess I'll change my reading to "only STM knows and this part was either half-cut down and rushed to production without updating all the docs, half-finished, both, or something else entirely (engineer high on the job?)"20:33:54
@mbrossard:matrix.orgMathiasI think that compared to the other ST parts, the H743 (H753 and H750) got a enhanced "FS" peripheral: it supports 3 more bi-directional end-points and 3 times larger SRAM buffer (4K instead of 1.25K). Some of the implementation details (pure speculation on my part is that the FS is actually a copy paste of the HS) unfortunately leak in the SVD / register definitions.20:42:50
@mbrossard:matrix.orgMathiasWhich is why the "FS" port shows up as HS in some places20:44:12
@dirbaio:matrix.orgdirbaiothey're called OTG_HS/OTG_FS in the C hals, in stm32cube XMLs, and most PDFs20:44:38
@adamgreig:matrix.orgadamgreigit sounds like it's the HS silicon but without the ULPI interface, given the extra EPs and buffers20:52:36
@adamgreig:matrix.orgadamgreigmaybe they got a bogof from synopsys ;p20:52:53
@mbrossard:matrix.orgMathias
In reply to @dirbaio:matrix.org
they're called OTG_HS/OTG_FS in the C hals, in stm32cube XMLs, and most PDFs
In the SVD file the USB2 appears as OTG2_HS_* which is why explains why it appears as such in the Rust HAL (and in the usb_hs.rs). There are some remnants also in the C HAL where constant for the clock is named RCC_AHB1ENR_USB2OTGHSEN
21:13:19
@jamesmunns:beeper.comJames Munns
In reply to @dngrs:matrix.org
yeah I guess I'll change my reading to "only STM knows and this part was either half-cut down and rushed to production without updating all the docs, half-finished, both, or something else entirely (engineer high on the job?)"
Think of it like a 100M Ethernet MAC, but they only put a 10M phy on the front end. Digitally, it could do HS, but since the analog bit is only good for FS, it is limited to "slow back compat" mode only
21:30:32
@adamgreig:matrix.orgadamgreigmaybe more like a 1G MAC that only has RMII interface available, no RGMII21:37:01
@adamgreig:matrix.orgadamgreigwell21:37:03
@adamgreig:matrix.orgadamgreigand.. a built in phy for 100m... uhhhhh21:37:09
@adamgreig:matrix.orgadamgreigmaybe not lol21:37:18
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})Was this chip released on April 1?21:38:29
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost})* Was this chip released on April 1st?21:38:40
@dirbaio:matrix.orgdirbaioin ST headquarters it's always april 1st21:39:34
@dngrs:matrix.orgdngrs (spookyvision@{github,cohost}) They saw the Kodak calendar and thought "we need something like this" 21:45:36

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