| 2 Feb 2023 |
 dngrs (spookyvision@{github,cohost}) | (with an external PHY) | 20:29:46 |
 dirbaio | intentionally cut-down to save silicon costs I guess | 20:29:47 |
| dirbaio | and anyway | 20:29:58 |
| dirbaio | the distinction between "OTG FS" and "OTG HS but with only a FS PHY" is irrelevant | 20:30:13 |
| dirbaio | the registers and the driver for both are the same | 20:30:23 |
| dngrs (spookyvision@{github,cohost}) | yeah sorry if I'm derailing too much, I'm just trying to understand | 20:30:27 |
| dirbaio | just the HS one has a few more bits to enable HS stuff | 20:30:38 |
| dirbaio | so in practice it doesn't matter, all you care is "it can't do HS" | 20:31:20 |
| dngrs (spookyvision@{github,cohost}) | sure | 20:31:29 |
| dirbaio | hence why I was arguing the OTG_HS1 / OTG_HS2 naming is wrong | 20:31:33 |
| dngrs (spookyvision@{github,cohost}) | In reply to @dngrs:matrix.org
and/or "you could use it at HS speed if it had ULPI pins for that peripheral"? is this interpretation correct though? | 20:31:38 |
| dirbaio | no idea! | 20:31:55 |
| dngrs (spookyvision@{github,cohost}) | ha, ok | 20:31:59 |
| dirbaio | maybe? or maybe it's had that stuff optimized out of the silicon | 20:32:26 |
| dngrs (spookyvision@{github,cohost}) | yeah I guess I'll change my reading to "only STM knows and this part was either half-cut down and rushed to production without updating all the docs, half-finished, both, or something else entirely (engineer high on the job?)" | 20:33:54 |
 Mathias | I think that compared to the other ST parts, the H743 (H753 and H750) got a enhanced "FS" peripheral: it supports 3 more bi-directional end-points and 3 times larger SRAM buffer (4K instead of 1.25K). Some of the implementation details (pure speculation on my part is that the FS is actually a copy paste of the HS) unfortunately leak in the SVD / register definitions. | 20:42:50 |
| Mathias | Which is why the "FS" port shows up as HS in some places | 20:44:12 |
| dirbaio | they're called OTG_HS/OTG_FS in the C hals, in stm32cube XMLs, and most PDFs | 20:44:38 |
 adamgreig | it sounds like it's the HS silicon but without the ULPI interface, given the extra EPs and buffers | 20:52:36 |
| adamgreig | maybe they got a bogof from synopsys ;p | 20:52:53 |
| Mathias | In reply to @dirbaio:matrix.org
they're called OTG_HS/OTG_FS in the C hals, in stm32cube XMLs, and most PDFs In the SVD file the USB2 appears as OTG2_HS_* which is why explains why it appears as such in the Rust HAL (and in the usb_hs.rs). There are some remnants also in the C HAL where constant for the clock is named RCC_AHB1ENR_USB2OTGHSEN | 21:13:19 |
 James Munns | In reply to @dngrs:matrix.org
yeah I guess I'll change my reading to "only STM knows and this part was either half-cut down and rushed to production without updating all the docs, half-finished, both, or something else entirely (engineer high on the job?)" Think of it like a 100M Ethernet MAC, but they only put a 10M phy on the front end. Digitally, it could do HS, but since the analog bit is only good for FS, it is limited to "slow back compat" mode only | 21:30:32 |
| adamgreig | maybe more like a 1G MAC that only has RMII interface available, no RGMII | 21:37:01 |
| adamgreig | well | 21:37:03 |
| adamgreig | and.. a built in phy for 100m... uhhhhh | 21:37:09 |
| adamgreig | maybe not lol | 21:37:18 |
| dngrs (spookyvision@{github,cohost}) | Was this chip released on April 1? | 21:38:29 |
| dngrs (spookyvision@{github,cohost}) | * Was this chip released on April 1st? | 21:38:40 |
| dirbaio | in ST headquarters it's always april 1st | 21:39:34 |
| dngrs (spookyvision@{github,cohost}) | They saw the Kodak calendar and thought "we need something like this" | 21:45:36 |
