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stm32-rs

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Discussion and support for stm32-rs projects. History is publicly viewable. Bridged to #stm32-rs on Libera IRC. Code of conduct: https://www.rust-lang.org/conduct.html. Public logs: https://libera.irclog.whitequark.org/stm32-rs18 Servers

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17 Oct 2021
@theunkn0wn1:matrix.orgtheunkn0wn1will do!00:11:09
@robyoung:matrix.orgrobyoungHi, what is a good source of randomness to source a PRNG on an stm32f411? Are there any examples of setting this up?17:43:41
@newam:matrix.orgnewamFor non-secure RNG you can sample a floating ADC pin as a seed.17:58:35
@newam:matrix.orgnewamOtherwise there are built-in CSRNGs on some STMs, or you can use the ATSHA atmel chip to generate secure RNG externally.17:59:07
@robyoung:matrix.orgrobyoungBrilliant thanks! 🙇 A floating ADC pin is perfect for me. It doesn't need to be truly random and there's no RNG peripheral on the chip I have unfortunately.18:12:13
@ryan-summers:matrix.orgryan-summersHonestly, you can sample even non-floating ADC pins and accumulate the LSBs oftentimes, since the converter typically has noise built in, but again, generally not truly random18:30:33
@adamgreig:matrix.orgadamgreigCertainly not a bad idea to only use the lsb and take 32 readings if you need a 32 bit seed18:34:37
@adamgreig:matrix.orgadamgreigStill surprisingly predictable and vulnerable to external influence but a lot more likely to give a good non-secure seed than a single adc read18:35:11
18 Oct 2021
@pinealservo:matrix.orgpinealservo

from what i can tell, about half the pins are pulled up, the others pulled down.
when a button is pressed one of the pull ups and one of the pull downs are bridged.

I have seen some keypad readers that rely on voltage dividers and an ADC in the microcontroller to detect which keys are being pressed.

21:21:05
@pinealservo:matrix.orgpinealservoSeemed to be fairly common in stuff like small consumer electronics control panels, like on a VCR or DVD player.21:24:46
@pinealservo:matrix.orgpinealservoHere's a fun example of good-sized keypad hooked up to an ATtiny85: http://www.technoblogy.com/show?NGM21:42:48
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20 Oct 2021
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@burrbull:matrix.orgburrbullFixed https://github.com/stm32-rs/stm32f4xx-hal/issues/36616:31:29
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21 Oct 2021
@korken89:matrix.orgkorken89Hmm, I have noticed a weird thing when playing with STM32H735, it seems that the SRAM regions are powered down (SRAM1-3), so initializing the RAM causes hardfault. How does one generally go about enabling the RAMs before initialization?13:46:58
@korken89:matrix.orgkorken89 * Hmm, I have noticed a weird thing when playing with STM32H735, it seems that the SRAM regions are powered down (SRAM1-3), so initializing the RAM causes hardfault. How does one generally go about enabling the RAMs before initialization?13:49:57
@jordens:matrix.orgjordens either enable with assembly in pre_init (or whatever it's called) or enable in rust and then initialize (bss, data, text etc) manually in rust. 13:56:48
@korken89:matrix.orgkorken89Yeah, sounds like the main option to do it13:57:47
@korken89:matrix.orgkorken89I've been hunting in the datasheet if there was some OTP bit that always enabled the SRAMs13:58:06
@korken89:matrix.orgkorken89No luck :(13:58:12
@adamgreig:matrix.orgadamgreig korken89: i think sram1/2 are disabled by default, but axi-sram and dtcm are both always-on? so i've mostly seen dtcm or axi-sram used for stacks/"RAM" in memory.x 23:31:00
22 Oct 2021
@korken89:matrix.orgkorken89Thanks for the tip! I was playing around with having Ethernet storage in some of the RAMs but stumbled on them not being initialized05:04:59
@korken89:matrix.orgkorken89Ah right, it was because examples in the H7 HAL was using sram106:09:29
@korken89:matrix.orgkorken89I guess it's enabled in some H7s and not in others06:10:11

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