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stm32-rs

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Discussion and support for stm32-rs projects. History is publicly viewable. Bridged to #stm32-rs on Libera IRC. Code of conduct: https://www.rust-lang.org/conduct.html. Public logs: https://libera.irclog.whitequark.org/stm32-rs42 Servers

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25 May 2023
@firefrommoonlight:matrix.orgfirefrommoonlightYea, H5 seems p similar to H701:28:12
@firefrommoonlight:matrix.orgfirefrommoonlightWith some flash considerations from L501:28:24
@firefrommoonlight:matrix.orgfirefrommoonlightAnd the standard SVD idiosyncrasies that vary from chip to chip that you escape and I mitigate 01:29:15
@firefrommoonlight:matrix.orgfirefrommoonlightI haven't ops tested this one yet, but may use it in a future flight controller design01:29:38
@firefrommoonlight:matrix.orgfirefrommoonlightWould probably be a better choice than the G4s I'm using for the smaller/cheaper ones I have now01:30:07
@x-yl:matrix.orgx-ylWorking on a QSPI interface for stm32f4xx-hal and I was wondering where I might find the address for the QUADSPI memory-mapped range? grepping for 9000_0000 (which is the address on stm32f412) on the stm32-rs repo has no results so I'm not too sure where to look13:30:32
@burrbull:matrix.orgburrbull
In reply to @x-yl:matrix.org
Working on a QSPI interface for stm32f4xx-hal and I was wondering where I might find the address for the QUADSPI memory-mapped range? grepping for 9000_0000 (which is the address on stm32f412) on the stm32-rs repo has no results so I'm not too sure where to look
  1. crate::pac::QUADSPI::ptr() shoud point to peripheral.
  2. Do you plan to place it independent crate or inside stm32f4xx-hal?
  3. Have you looked at f7/h7/l4xx-hal. All of them already have its own implementation.
15:28:37
@burrbull:matrix.orgburrbull
In reply to @x-yl:matrix.org
Working on a QSPI interface for stm32f4xx-hal and I was wondering where I might find the address for the QUADSPI memory-mapped range? grepping for 9000_0000 (which is the address on stm32f412) on the stm32-rs repo has no results so I'm not too sure where to look
*
  1. crate::pac::QUADSPI::ptr() shoud point to peripheral.
  2. Do you plan to place it independent crate or inside stm32f4xx-hal?
  3. Have you looked at f7/h7/l4xx-hal. Each of them already have its own implementation.
15:28:57
@dirbaio:matrix.orgdirbaio

crate::pac::QUADSPI::ptr() shoud point to peripheral.

that's the qspi regs, not the qspi memory-mapped region

15:31:48
@dirbaio:matrix.orgdirbaioThe 0x9000_0000 addr is not in the PAC, I'd just hardcode it15:32:09
@x-yl:matrix.orgx-yl
  1. Yeah it's just the control register, not the actual memory mapped region
  2. Inside stm32f4xx-hal
  3. Yeah my implementation is largely based on the l4 hal but I don't think any of them support putting the QSPI in memory mapped mode
15:51:48
@x-yl:matrix.orgx-yl
In reply to @dirbaio:matrix.org
The 0x9000_0000 addr is not in the PAC, I'd just hardcode it
Cool, I'll do that then
15:52:05
@burrbull:matrix.orgburrbull
In reply to @x-yl:matrix.org
  1. Yeah it's just the control register, not the actual memory mapped region
  2. Inside stm32f4xx-hal
  3. Yeah my implementation is largely based on the l4 hal but I don't think any of them support putting the QSPI in memory mapped mode
This is partially adopted l4 file: https://github.com/stm32-rs/stm32f4xx-hal/blob/62fcd164fa0ceddc2729ab5ac445421066d9aa65/src/qspi/l4.rs
16:02:10
@x-yl:matrix.orgx-ylAh so is this already a WIP then?16:14:28
@burrbull:matrix.orgburrbullno. just experiment. all in your hands16:15:24
@x-yl:matrix.orgx-ylAh okay then, you can look forward to a PR soonish then :)16:16:22
26 May 2023
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27 May 2023
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28 May 2023
@x-yl:matrix.orgx-yl burrbull: I was wondering about this change: https://github.com/stm32-rs/stm32f4xx-hal/commit/6650964c084cb8f3cb5d6ad8e006f22bcfb4b44b. What's the purpose of splitting the new function for dual flash? is it just so that we can have impl Into on the argument? 11:08:42
@burrbull:matrix.orgburrbullизображение.png
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11:16:37
@burrbull:matrix.orgburrbullmostly yes. 11:16:47
@burrbull:matrix.orgburrbull Even without impl Into I'd prefer to see explicit pin types in new 11:22:16
@x-yl:matrix.orgx-ylFair enough, yeah, using the type system to enforce pin assignments is very cool but can be a bit confusing to figure out 11:25:58
@burrbull:matrix.orgburrbullsometimes yes, but for now there is only 2 variants: single and dual flash11:27:27
@burrbull:matrix.orgburrbull * sometimes yes, but for now there are only 2 variants: single and dual flash11:28:58
1 Jun 2023
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