| 18 May 2022 |
 therealprof | For instance if the bit is ressembling: read buffer full, you can clear it by reading the data from the data register. If the bits is ressembling: send buffer empty, then you "fix" that by putting data into the output register. | 08:04:31 |
 henrikssn | Oh, I see, thanks that makes it clear | 08:09:13 |
| henrikssn | I'll make another dive into the reference manual then :) | 08:09:23 |
 Hanno Braun | Hey folks! I've been going through my drawers, clearing out stuff I'm unlikely to use. I found lots of STM32 boards, and I'm happy to donate them to anyone who will use them. Here's the list:
- 2x STM32 F0 Discovery
- 1x STM32F072 Discovery kit
- 2x STM32F303 Discovery kit
- 1x STM32F746 Nucleo-144
- 2x STM32 LoRa and Sigfox Discovery kit
- 2x STM32L433 Nucleo-64
- 1x STM32L476 Discovery kit
Most are just lightly used or completely unused, the rest I used daily for client projects. Not sure they all work; I have vague memories about having problems with some, and don't remember if I threw those out.
I'd prefer sending as few packages as possible, so if anyone here can use a lot of them, or maybe has some local meetup where they can give them away, that would be great! If you're interested, feel free to send me your address in a private chat, or shoot me an email.
| 08:39:24 |
| henrikssn | I wrote a little SPI demo, where I put the incoming RX data into a FIFO buffer and send it back out on TX | 15:02:57 |
| henrikssn | I have no problems doing that at 7.8Mbit/sec even with a measly F411 at 100MHz | 15:03:28 |
| henrikssn | * I have no problems doing that at 7.8Mbit/sec even with a F411 at measly 100MHz | 15:03:46 |
| henrikssn | * I wrote a little SPI slave demo, where I put the incoming RX data into a FIFO buffer and send it back out on TX | 15:05:14 |
| therealprof | I wouldn't expect this to be a problem. I've been pushing out north of 20Mbit/s of data via SPI on such a chip without a problem (without DMA). | 15:43:09 |
| henrikssn | Yeah I guess I had no idea of what I should expect | 15:45:30 |
| henrikssn | My demo is with DMA and 32 byte buffers | 15:45:49 |
| henrikssn | I use two bbqueue's for rx/tx and just echoed the data on the other end | 15:46:25 |
 firefrommoonlight | Hey all. I noticed some (all?) STM32s have configurable "option bytes" for configuring flash memory. Is there a way for SVD2Rust /PACs to handle this? Maybe they do already? Thank you | 15:54:55 |
| firefrommoonlight | For example, configuring nboot0, dbank, nrst mode etc | 15:55:30 |
| firefrommoonlight | I'm guessing out of scope? They're in a weird place and have diff write procedures from normal rega | 15:56:38 |
| firefrommoonlight | * I'm guessing out of scope? They're in a weird place and have diff write procedures from normal regs | 15:56:43 |
| firefrommoonlight | I guess they're part of the flash memory itself? | 15:57:05 |
 dirbaio | yeah it's kind of a "weird flash" | 16:00:09 |
| dirbaio | putting them in the PAC wouldn't work because you have to do special stuff to write them yep | 16:00:51 |
| firefrommoonlight | I'll probably just do a raw reg write for now | 16:05:56 |
| firefrommoonlight | Also lol@ some G4 variants being configurable as 2 or 1 bank depending on how you set one of those options | 16:06:23 |
 adamgreig | are the option byte registers not in the PAC as part of the flash peripheral? | 16:38:13 |
| adamgreig | I'm pretty sure they are all accessed as registers inside the flash peripheral | 16:39:19 |
| dirbaio | FLASH has regs to unlock writing to option regs | 16:39:36 |
| dirbaio | but option regs themselves are at 0x1fffsomething which is not the FLASH regs | 16:39:48 |
| adamgreig | on stm32h7 at least there's registers in the flash memory space for programming the option registers | 16:40:49 |
| adamgreig | like FLASH_BOOT7_PRGR | 16:40:54 |
| dirbaio | ohh 🤔 | 16:42:56 |
| adamgreig | but yea, looks like my f0 code just knows about the magic addresses to write to instead | 16:44:13 |
| firefrommoonlight | Interesting re H7 | 19:05:18 |
