| 16 Apr 2024 |
 CyberSeal πΊπΈπ±π | Download riscv-crypto-spec-scalar-v1.0.0-rc2.pdf | 12:32:35 |
| CyberSeal πΊπΈπ±π | do you want a herd of goats or do you prefer it that way? | 12:59:50 |
| CyberSeal πΊπΈπ±π | anyway, enjoy this doc, it is efficient for newbies. π€πΌ | 13:02:10 |
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| 17 Apr 2024 |
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| 18 Apr 2024 |
 Shadow | Thank you | 03:26:52 |
| CyberSeal πΊπΈπ±π | Redacted or Malformed Event | 05:40:11 |
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| CyberSeal πΊπΈπ±π | https://gms.tf/riscv-vector.html | 22:50:05 |
| CyberSeal πΊπΈπ±π | * useful and practical knowledge. https://gms.tf/riscv-vector.html | 22:51:52 |
| 20 Apr 2024 |
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| 23 Apr 2024 |
| CyberSeal πΊπΈπ±π changed their display name from Minimaul to Minimaul πΊπΈπ±π. | 17:46:35 |
| 24 Apr 2024 |
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 olku | Hi everyone.
If someone read/worked with AIA spec (sorear: ) how eidelivery and eithreshold of different interrupt files can be accessed simultaneously:
1. At the old interrupt file, save to memory the values of registers eidelivery and eithreshold,
and set eidelivery = 0.
2. At the new interrupt file, set eidelivery = 0, and zero all implemented interrupt-pending
bits (the eip array).
....
4. At the old interrupt file, dump to memory all implemented interrupt-pending and interrupt-
enable bits (the eip and eie arrays). After this step is done, the old interrupt file is no longer
in use.
According to this steps it should be a way to access eip, eithreshold, edelivery, etc of different interupt files.
| 15:40:53 |
| olku | as far as i understand the register mentioned above are accessed through csr instructions | 15:42:49 |
|  ΠΠ»Π΅ΠΊΡΠ°Π½Π΄Ρ Π ΡΠ΄Π°Π»ΡΠ² joined the room. | 16:29:33 |
 Daniel aka CyReVolt π’ | lmk if anyone is interested in the small CVITek/Sophgo SoCs, CV1800B (Milk-V Duo board), SG2002 (Duo 256M), SG2000 (Duo S); I have started writing a nice tool to load bare metal code for direct execution, and I have an initial draft for plarform init code (oreboot) | 17:10:13 |
 Elyasaf Yechezkeli | Hey, CyReVolt - it may help me, can you share it? | 17:40:47 |
| Daniel aka CyReVolt π’ | In reply to @telegram_356649424:t2bot.io
Hey, CyReVolt - it may help me, can you share it? I am looking for contributors, not consumers. | 18:06:24 |
| Daniel aka CyReVolt π’ | Well, collaborations. | 18:06:36 |
| Daniel aka CyReVolt π’ | * Well, collaborators. | 18:08:20 |
| Elyasaf Yechezkeli | Ohh, not suitable for me right now, but have a good luck! | 18:51:57 |
 Alexander Gorodnev | In reply to @CyReVolt:matrix.org
I am looking for contributors, not consumers. What itβs expected from a contributor? | 19:05:48 |
| Daniel aka CyReVolt π’ | In reply to @telegram_39714908:t2bot.io
What itβs expected from a contributor? Translating and simplifying the DRAM init would be great, can probably be parameterized and shared between the platforms / SoCs. | 20:59:55 |
| Daniel aka CyReVolt π’ | Seeing if things need to differ for booting from different sources is another open task: USB/UART vs SPI flash (NOR) vs SD card or EMMC. | 21:00:59 |
| Daniel aka CyReVolt π’ | Boot flow design discussions also help, dumping the mask ROM and documenting it, etc.. | 21:01:53 |
