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RISC-V

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RISC-V is a free and open ISA. Part of #riscv:matrix.org. Bridged to Telegram: https://t.me/riscv. Unofficial.22 Servers

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30 Jan 2023
@volhard:monero.socialvolhardLol20:23:27
@volhard:monero.socialvolhardThough I don't get why you need a syscall at all.20:23:31
@volhard:monero.socialvolhardJust set an 'enter' bit for an enterable page, and you can enter it from its start, which can set up defensive checks.20:24:25
@volhard:monero.socialvolhardBonus: No more ASLR20:25:30
@volhard:monero.socialvolhard* Something that lets you restrict executable instructions on a page-level, perhaps using a bit mask. At least you don't go all or none with privilege in that case (just focus on securing whatever is managing pages, which is way smaller than the whole kernel).20:33:16
@volhard:monero.socialvolhardAnd most code are just helpers, so they don't need access checks to begin with - just the right privilege.20:35:18
@volhard:monero.socialvolhard* And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can gate power using the privilege bits as hint.20:36:15
@volhard:monero.socialvolhard* And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can power gate using the privilege bits as hint.20:36:45
@volhard:monero.socialvolhard* And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can power gate using the privilege as hint.20:39:11
@volhard:monero.socialvolhard* Just set an 'enter' bit for an enterable page, and you can enter from the page's starting address, which can set up defensive checks.20:43:03
@telegram_512728571:tchncs.deBruce Hoult (Telegram)The RISC-V standard privileged architecture is a module, completely distinct from the instruction set itself. It’s replaceable. Grab an FPGA and an existing core and DO IT.20:50:34
@volhard:monero.socialvolhardWill look into it.20:52:01
@volhard:monero.socialvolhard* I'm planning on a 16-bit VM for now.20:59:12
@volhard:monero.socialvolhard* I'm planning on a 16-bit VM for now (never touched an FPGA before).20:59:54
@volhard:monero.socialvolhard* I'm planning on a 16-bit VM for now (never touched an FPGA before, though for most part I couldn't afford one until recently.).21:00:38
@volhard:monero.socialvolhard* I'm planning on a 16-bit VM for now (never touched an FPGA before, though the main reason is that I couldn't afford one until recently).21:00:44
@volhard:monero.socialvolhard* I'm planning a 16-bit VM for now (never touched an FPGA before, though the main reason is that I couldn't afford one until recently).21:01:17
@volhard:monero.socialvolhard* I'm planning a 16-bit VM for now (never touched an FPGA; though the main reason is that I couldn't afford one until recently).21:02:38
1 Feb 2023
@telegram_492445660:tchncs.dePierce Andjelkovic (Telegram) https://www.youtube.com/live/EcQLijZwYCU 09:10:59
@telegram_41219153:tchncs.dejose gonzalez (Telegram) joined the room.11:43:06
@telegram_41219153:tchncs.dejose gonzalez (Telegram)
In reply to Pierce Andjelkovic (Telegram)
https://www.youtube.com/live/EcQLijZwYCU
is it a risc-v arch?
11:43:06
@telegram_41219153:tchncs.dejose gonzalez (Telegram) changed their profile picture.11:43:07
@telegram_472898010:tchncs.deLekKit (Telegram)
In reply to jose gonzalez (Telegram)
is it a risc-v arch?
No
11:52:44
@telegram_512728571:tchncs.deBruce Hoult (Telegram) /me прячется от сумасшедшего Ивана 12:26:01
@telegram_5570351899:tchncs.deMax ⸙ꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋᅠࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩ (Telegram)Redacted or Malformed Event12:30:10
@rvstitch:tchncs.deStitch RV
In reply to @telegram_41219153:tchncs.de
is it a risc-v arch?
This e2k
14:40:42
@testman42:matrix.orgtestman changed their display name from testman to testman42.15:17:18
2 Feb 2023
@telegram_1494262433:tchncs.deJavad (Telegram) changed their profile picture.07:51:40
@testman42:matrix.orgtestman changed their display name from testman42 to testman.10:37:24
@royills:matrix.orgroyills joined the room.17:24:25

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