| 30 Jan 2023 |
 volhard | Lol | 20:23:27 |
| volhard | Though I don't get why you need a syscall at all. | 20:23:31 |
| volhard | Just set an 'enter' bit for an enterable page, and you can enter it from its start, which can set up defensive checks. | 20:24:25 |
| volhard | Bonus: No more ASLR | 20:25:30 |
| volhard | * Something that lets you restrict executable instructions on a page-level, perhaps using a bit mask. At least you don't go all or none with privilege in that case (just focus on securing whatever is managing pages, which is way smaller than the whole kernel). | 20:33:16 |
| volhard | And most code are just helpers, so they don't need access checks to begin with - just the right privilege. | 20:35:18 |
| volhard | * And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can gate power using the privilege bits as hint. | 20:36:15 |
| volhard | * And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can power gate using the privilege bits as hint. | 20:36:45 |
| volhard | * And most code are just helpers, so they don't need access checks to begin with - just the right privilege (arithmetic, boolean ops, ...). Also the processor can power gate using the privilege as hint. | 20:39:11 |
| volhard | * Just set an 'enter' bit for an enterable page, and you can enter from the page's starting address, which can set up defensive checks. | 20:43:03 |
 Bruce Hoult (Telegram) | The RISC-V standard privileged architecture is a module, completely distinct from the instruction set itself. It’s replaceable. Grab an FPGA and an existing core and DO IT. | 20:50:34 |
| volhard | Will look into it. | 20:52:01 |
| volhard | * I'm planning on a 16-bit VM for now. | 20:59:12 |
| volhard | * I'm planning on a 16-bit VM for now (never touched an FPGA before). | 20:59:54 |
| volhard | * I'm planning on a 16-bit VM for now (never touched an FPGA before, though for most part I couldn't afford one until recently.). | 21:00:38 |
| volhard | * I'm planning on a 16-bit VM for now (never touched an FPGA before, though the main reason is that I couldn't afford one until recently). | 21:00:44 |
| volhard | * I'm planning a 16-bit VM for now (never touched an FPGA before, though the main reason is that I couldn't afford one until recently). | 21:01:17 |
| volhard | * I'm planning a 16-bit VM for now (never touched an FPGA; though the main reason is that I couldn't afford one until recently). | 21:02:38 |
| 1 Feb 2023 |
 Pierce Andjelkovic (Telegram) | https://www.youtube.com/live/EcQLijZwYCU | 09:10:59 |
|  jose gonzalez (Telegram) joined the room. | 11:43:06 |
| jose gonzalez (Telegram) | In reply to Pierce Andjelkovic (Telegram)
https://www.youtube.com/live/EcQLijZwYCU is it a risc-v arch? | 11:43:06 |
| jose gonzalez (Telegram) changed their profile picture. | 11:43:07 |
 LekKit (Telegram) | In reply to jose gonzalez (Telegram)
is it a risc-v arch? No | 11:52:44 |
| Bruce Hoult (Telegram) | /me прячется от сумасшедшего Ивана | 12:26:01 |
 Max ⸙ꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋꠋᅠࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩࣩ (Telegram) | Redacted or Malformed Event | 12:30:10 |
 Stitch RV | In reply to @telegram_41219153:tchncs.de
is it a risc-v arch? This e2k | 14:40:42 |
|  testman changed their display name from testman to testman42. | 15:17:18 |
| 2 Feb 2023 |
|  Javad (Telegram) changed their profile picture. | 07:51:40 |
| testman changed their display name from testman42 to testman. | 10:37:24 |
|  royills joined the room. | 17:24:25 |
