In reply to @raitobezarius:matrix.org
It's bureaucry oriented development

In reply to @raitobezarius:matrix.org
I'd argue though that RISC V specs are more technical than bureaucratic

In reply to @CyReVolt:matrix.org

That is what the hyperscalers do with LinuxBoot.
Google, Meta, ByteDance etc use it to speed up their infra's boot processes, gain easier customizability and get rid of attack surface.

We also use it together with oreboot, and you can put it on top of U-Boot SPL + SBI on RISC-V.

I'll be giving a talk later today, a RISC-V Tech Session, where I elaborate on bootloaders and solution options. A demo will be part of it.

Hi there.

I would like to ask you about the correct way to get an instruction length somewhere in hypervisor/kernel.
I have the following code:

#define GET_INSN_LENGTH(insn)                               \
    (((insn) & INSN_LENGTH_MASK) == INSN_LENGTH_32 ? 4 : 2) \

uint32_t read_instr(unsigned long pc)
{
    uint16_t instr16 = *(uint16_t *)pc;

    if ( GET_INSN_LENGTH(instr16) == 2 )
       return (uint32_t)instr16;
    else
       return *(uint32_t *)pc;
}

The code above doesn't look safe as it requires double-read ( so instruction can be changed during this reads ).

Another one question how hardware is supposed to deal with this situation. Can it indeed fetch in 16-bit quantities?
It looks like it is the smallest possible amount of bit in case when we have compressed ISA.

My guess was that it reads a i-cache size amount of bits and then pipeline tracks whether an insturction is 16 or 32 bit
but still doesn't clear what h/w does in case an instruction span i-cacheline boundary?

from the RISCV ISA doc:

1.2 Instruction Length Encoding
The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit
boundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensions
with variable-length instructions, where each instruction can be any number of 16-bit instruction
parcels in length and parcels are naturally aligned on 16-bit boundaries. The standard compressed
ISA extension described in Chapter 12 reduces code size by providing compressed 16-bit instructions
and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on
any 16-bit boundary to improve code density

but does it mean that h/w will always fetch 16-bit, then check length of an instruction and etc?