Alright, you can try out what's currently in the repo.
Plug in a Duo S, if you have an EMMC or SD card, press the RECOVER + RESET buttons, and then just cargo run --release -- info, and you will see oreboot's hello message on the UART:

C.SCS/0/0.WD.URPL.USBI.USBK.USBD.BS/USB.PS.USBB.USBL.PE.BS.USBK.USBL.BE.J.B


oreboot 🦀 bt0
RISC-V arch 00000000
RISC-V core vendor: unknown (0x05b7)
RISC-V implementation: unknown (0x00000000)
RISC-V hart ID 0
boot src: USB
[bt0] Jump to main stage @80200000

for verbosity:

RUST_LOG=debug cargo run --release -- info

In reply to @olku:matrix.org

Hi everyone.

If someone read/worked with AIA spec (sorear: ) how eidelivery and eithreshold of different interrupt files can be accessed simultaneously:

1. At the old interrupt file, save to memory the values of registers eidelivery and eithreshold,
and set eidelivery = 0.
2. At the new interrupt file, set eidelivery = 0, and zero all implemented interrupt-pending
bits (the eip array).
....
4. At the old interrupt file, dump to memory all implemented interrupt-pending and interrupt-
enable bits (the eip and eie arrays). After this step is done, the old interrupt file is no longer
in use.

According to this steps it should be a way to access eip, eithreshold, edelivery, etc of different interupt files.

In reply to @CyReVolt:matrix.org
lmk if anyone is interested in the small CVITek/Sophgo SoCs, CV1800B (Milk-V Duo board), SG2002 (Duo 256M), SG2000 (Duo S); I have started writing a nice tool to load bare metal code for direct execution, and I have an initial draft for plarform init code (oreboot)

In reply to @telegram_512728571:t2bot.io
What’s the status on the original Duo?

I've figured that one could trigger its fallback to the mask ROM loader by shorting the pads that would hold the second button on the IO board. The SoC is very similar, so the same code may already run; I just need to compare the SRAM and UART base addresses, will then do a test later.

I have figured out the header format now for creating a bootable image. Will adjust the tool over the next days to get rid of fixtures, then we can use it to load arbitrary binaries on either SoC, i.e. iteratetively develop the actual code. :)

A little help from a screwdriver 🪛 does that job.

Otherwise, without the IO board, pulling the second ADC pin high with a resistor to 3V should also do.

In reply to @sorear:matrix.org
the implication is that between step 1 and 2 you migrate to a different hart, since these instructions are for when guests migrate. you could in principle migrate a guest to the same hart with a different VGEIN, but there's no real reason to do that

In reply to @sorear:matrix.org
the instructions apply everywhere, some instructions have to apply to the old interrupt file, some to the new

In reply to @CyReVolt:matrix.org

A little help from a screwdriver 🪛 does that job.

Otherwise, without the IO board, pulling the second ADC pin high with a resistor to 3V should also do.

dama@orangelemp:~/f/M/D/cvitek-fsbl (main|🧹  🐾 )
🐢 ➤ fdfind '\.ld.S'
make_helpers/get_macros.ld.S
plat/cv180x/bl2/bl2.ld.S
plat/cv181x/bl2/bl2.ld.S
dama@orangelemp:~/f/M/D/cvitek-fsbl (main|🧹  🐾 )
🐢 ➤ less plat/cv180x/bl2/bl2.ld.S
dama@orangelemp:~/f/M/D/cvitek-fsbl (main|🧹  🐾 )
🐢 ➤ rg BL2_BASE plat/cv180x/                                                                                                                                                             7.893s
plat/cv180x/include/mmap.h
48:#define BL2_BASE (VC_RAM_BASE)

plat/cv180x/bl2/bl2.ld.S
19:    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_SIZE
24:    . = BL2_BASE;
26:           "BL2_BASE address is not aligned on a page boundary.")
81:    ASSERT(. <= (BL2_BASE + BL2_SIZE), "BL2 image has exceeded its limit.")
dama@orangelemp:~/f/M/D/cvitek-fsbl (main|🧹  🐾 )
🐢 ➤ rg VC_RAM_BASE plat/cv180x/
plat/cv180x/include/mmap.h
48:#define BL2_BASE (VC_RAM_BASE)

plat/cv180x/include/platform_def.h
296:    #define VC_RAM_BASE 0x3BC00000 // Shadow_vc_mem

In reply to @telegram_425741966:t2bot.io
Доброго времени суток
Есть (моя) небольшая программа на C#, примерно 500 строк
Ищу специалиста кто поможет переложить её на RISK-V. И оттестировать хотя бы в эмуляторе.
Сейчас ищу кто сможет это сделать. Оплата поэтапно. Вопросы в личку .

In reply to @CyReVolt:matrix.org
sent an image.

In reply to @olku:matrix.org
do you mean that I have to send an IPI to a hart to which guest cpu is migrated to? But then it would be needed to do another one IPI to old hart ( because in the step 4 it is mentioned that it is needed to some things related to old interrupt file )

In reply to @olku:matrix.org
but to access EIDELIVERY for example, I have to be on IMSIC's hart of which i want to read/write EIDELIVERY. sounds like that it should be a mechanism how to get to another hart do something and back to old hart.

In reply to @sorear:matrix.org
yes? like any other hart register, it's local and you need to use an IPI or something similar. there's no hardware mechanism for forcing another hart to save its float or vector registers or do a sfence.vma

In reply to @CyReVolt:matrix.org
https://github.com/orangecms/sg_boot this

Alright, the tool is now flexible so you can run your own code.
I've committed two prebuilt simple oreboot print binaries.

For Duo 256M and Duo S:

cargo run --release -- run oreboot_sg200x.bin

For older Duo:

cargo run --release -- run oreboot_cv1800b.bin

or provide your own binary :)