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RISC-V

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8 Oct 2021
@skallwar:matrix.orgSkallwar (Esteban Blanc)

Hi guys. I'm writing an operating system (supervisor mode) in Rust for RISC-V in my free time. I'm trying to handle trap now.

I'm trapping correctly in direct mode but when executing sret instruction, I'm going directly back to my trap handler, without going back to the address stored in sepc.
I'm writing to 0x0 to test my trap_handler.

Have you an idea on what's going on ?

12:24:29
9 Oct 2021
@telegram_984517860:tchncs.deKunal VSD (Telegram) VSDOpen2021 Tutorial 3 - Most Exciting - Bandgap Tapeout using Sky130

Now here's a 2-day tutorial which is both for freshers and professionals
Why freshers? Bandgap IP design is the most basic one, if you want to learn and excel in Analog Design
Why professionals? Non-Analog professionals would love the way the content has been structured, thereby, enabling curious physical designers, STA engineers to see how an IP looks like

This time VSDOpen2021 third tutorial invites everyone and anyone who wants to learn about analog IP design from scratch and learn from Bandgap expert Dr. Saroj Rout, Adjunct.Prof. and Asst. Prof. Santunu Sarangi from Silicon Institute of Technology

Analog Design Experts - Feel free to join to encourage freshers and look at our internship cum workshop model

Overview:

This course will be an in-depth introduction to Bandgap Reference (BGR) design and layout using open-source EDA tools (ngspice & Magic) and Google’s Skywater 130nm (SKY130) open-source process design kit (PDK). The course will focus on intuitive understanding of the concepts involved in designing a BGR with real-world specifications and complete hands-on practice using the open-source EDA tools. During the 100 min course, the participant will start with the basic principles of BGR circuit, design, simulate and layout a complete industry-grade BGR – all of that in just 100 mins!

Course Curriculum:

Day 1 – BGR Theory and Lab setup

Why temperature-independent voltage/current references for ICs
Realization of BGR voltage reference.
Circuit realization of a self-biased BGR and introduction to PTAT/CTAT current source

Day 2 – BGR Labs and post-layout simulations

BGR components circuit simulations
Steps to combine BGR sub-circuits and BGR full design simulation
Post Layout simulations
Steps to combine layouts

Features - Low cost ($25), 2-day, cloud lab based workshop
Timings - You can login at your own convenient time during 24-hrs duration of the workshop and start with lectures/labs at your own pace
Workshop Start date - 20th October, 11:59pm IST
Workshop End date - 22nd October, 11:59pm IST

Registration link-
Indian Participants-
https://pages.razorpay.com/bandgapinr

International Participants-
https://pages.razorpay.com/bandgapdollar

All the best and happy learning
06:52:07
@telegram_984517860:tchncs.deKunal VSD (Telegram)Download 2021-0918-VSD-PPT.gif.mp406:52:21
@telegram_482592638:tchncs.dehandicraftsman (Telegram)
In reply to Kunal VSD (Telegram)
sent a video
Hi, do you know any open source (or just free or, goddamn, easily downloadable) verilog/vhdl a/ams simulators?
07:11:46
@telegram_482592638:tchncs.dehandicraftsman (Telegram) changed their profile picture.07:11:51
@telegram_519513694:tchncs.deÁbel (Telegram)
In reply to handicraftsman (Telegram)
Hi, do you know any open source (or just free or, goddamn, easily downloadable) verilog/vhdl a/ams simulators?
http://ngspice.sourceforge.net/adms.html
07:15:02
@telegram_984517860:tchncs.deKunal VSD (Telegram)
In reply to handicraftsman (Telegram)
Hi, do you know any open source (or just free or, goddamn, easily downloadable) verilog/vhdl a/ams simulators?
Iverilog and gtkwave for verilog
07:20:19
@telegram_265273393:tchncs.deJayaramm (Telegram)Which FPGA is good to get started? Any inputs on this14:32:30
@nsmlzl:matrix.orgNiklasghdl for VHDL15:19:11
10 Oct 2021
@chile09:matrix.orgchile09 joined the room.21:09:09
11 Oct 2021
@telegram_1518482081:tchncs.dejack hlhl (Telegram) joined the room.14:49:23
@telegram_1518482081:tchncs.dejack hlhl (Telegram) changed their display name from telegram_1518482081 to jack hlhl (Telegram).14:49:24
12 Oct 2021
@chodot:matrix.orgJulius joined the room.07:54:44
@chile09:matrix.orgchile09can RISC-V be run with open firmware?21:07:48
13 Oct 2021
@telegram_636787316:tchncs.dekorpse (Telegram)
In reply to Jayaramm (Telegram)
Which FPGA is good to get started? Any inputs on this
iCEBreaker
02:16:23
@acleverdisguise:matrix.orgA Man With A Clever Disguise
In reply to @telegram_636787316:tchncs.de
iCEBreaker
Is that the dev board with the iCE40 UltraPlus 5K?
07:21:10
@telegram_636787316:tchncs.dekorpse (Telegram)
In reply to @acleverdisguise:matrix.org
Is that the dev board with the iCE40 UltraPlus 5K?
Yep
07:21:35
@acleverdisguise:matrix.orgA Man With A Clever DisguiseThere's also an "iCESugar" board from Muse that has the same chip.07:32:29
@acleverdisguise:matrix.orgA Man With A Clever Disguisehttps://www.aliexpress.com/item/4001201771358.html07:33:34
@telegram_636787316:tchncs.dekorpse (Telegram)Yes, but not so convenient to work with07:51:15
@telegram_984517860:tchncs.deKunal VSD (Telegram) Next Sky130 RTL2GDS workshop dates

Many of you missed our previous RTL2GDS workshops, so here are the dates for next Sky130 RTL2GDS workshop series. All workshops will happen in parallel from 27th October'21 to 31st October'21, so make sure you join only 1 out of 4. You can join the others in next round

Here's the link for individual workshop registration details

Verilog RTL design and synthesis:
https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/

CMOS Circuit design and SPICE simulations (most important of all):
https://www.vlsisystemdesign.com/cmos-circuit-design-spice-simulation-using-sky130-technology/

Physical Design (from basics to advanced):
https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/

Physical Verification:
https://www.vlsisystemdesign.com/physical-verification-using-sky130/

All the best and happy learning
15:06:35
@telegram_984517860:tchncs.deKunal VSD (Telegram)image.jpeg
Download image.jpeg
15:06:46
16 Oct 2021
@telegram_2098679071:tchncs.deCão Preto (Telegram) joined the room.02:21:11
@telegram_2086338029:tchncs.deAndres U (Telegram) joined the room.05:09:14
@telegram_984517860:tchncs.deKunal VSD (Telegram) VSDOpen PLL/OSU180nm tutorial - Last 36 hours left for registration

This is a gentle reminder - VSDOpen First Tutorial (for the student, of the student and by the student) on PLL using OSU180nm registration closes in 36-hours. For anyone, who want to *understand VLSI field from scratch*, this is the best one, as it is delivered by a student who has gone through the whole VSD learning process and has offers from 3-4 semiconductor companies

Note - Jobs are not main focus of VSD, but they are an excellent by-product of VSD tutorials, workshops and hardware design programs

He was a true fresher, when he joined VSD couple of years back, but the 5-stage process which he has gone through in addition to his own dedication, hard work and sincerity will make you believe that even if you don't know anything about this field and really want to be a part of this ever growing exciting field, it is definitely possible.

One key thing about VSD process, workshop and tutorials - 5% theory, 95% labs - you will be given cloud lab instances to practice your design simulations. So no need to install any tools on your laptop. All you need is a VSD Login ID

Here's the registration link:
Indian Participant
https://pages.razorpay.com/pllosu180

International Participant
https://pages.razorpay.com/plldollar

All the best and happy learning

Other tutorials - Visit below page
https://www.vlsisystemdesign.com/registration/
07:12:21
17 Oct 2021
@telegram_880953545:tchncs.deSJ (Telegram) joined the room.14:17:09
18 Oct 2021
@telegram_984517860:tchncs.deKunal VSD (Telegram) VSDOpen FPGA tutorial - Last 10 hours left for registration

Another democratic workshop - Digital design using virtual FPGA - by Bala Dinesh, BTech IIT Madras

He is someone with whom all freshers and all students can connect to. Why? His journey in the world of FPGA is really amazing.

Bala successfully conducted Circuit Design Challenge and Arduino Programming Contest with around 60 teams. He Conducted the Introduction to FPGA on Embedded Systems workshop for the annual tech fest of IIT Madras, SHAASTRA 2021. Taught the basics of FPGA programming and Verilog and finally built a Whack-A-Mole game using FPGA, LEDs, Slide switches and seven-segment displays. One of the most successful workshops with over 100 participants participated virtually.

Finally, he contributed to the FOSSi Foundation through Google Summer of Code 2021. This project aims to provide Virtual FPGA simulations using VIZ Feature on the Makerchip platform to offer an easy path for the migration of physical lab classes by mimicking the physical lab experience

So, all freshers, don't think much. Here's you last chance to enroll and start you initial work on virtual FPGA, in minutes

Features - Low cost ($10), 1-day, cloud lab based workshop
Timings - You can login at your own convenient time during 24-hrs duration of the workshop and start with lectures/labs at your own pace
Workshop Start date - 19th October, 11:59pm IST
Workshop End date - 20th October, 11:59pm IST

Registration link (last 10 hours)-

Indian Participants
https://pages.razorpay.com/fgpainr

International Participants
https://pages.razorpay.com/vsdopenfgpa

All the best and happy learning
08:19:03
@telegram_984517860:tchncs.deKunal VSD (Telegram)Download 130665759-9894f0de-c058-4075-a990-2dee094123b4.gif.mp408:19:24
19 Oct 2021
@telegram_984517860:tchncs.deKunal VSD (Telegram) Last 12hrs - VSDOpen Sky130 tapeout tutorial For Analog Design aspirants

For so many years, you have been asking for Analog Design Workshop by Analog Expert - There you go. Here's tapeout quality Bandgap Design using Sky130 2-day cloud lab based tutorial by Dr. Saroj Rout Adjunct. Prof. and Asst. Prof. Santunu Sarangi from Silicon Institute of Technology who has spent many years designing bandgap IP using XFAB. It was an honour to have them on board and share their entire learning on the VSD-IAT platform. Guess what - This tutorial is totally hands-on from circuit to layout, as seen from images, and all of them using Skywater 130nm PDK, so it's completely manufacturable

Features
- Low cost ($25), 2-day, cloud lab based workshop
Timings - You can login at your own convenient time during 24-hrs duration of the workshop and start with lectures/labs at your own pace
Workshop Start date - 20th October, 11:59pm IST
Workshop End date - 22nd October, 11:59pm IST

Registration link Last 12hours
Indian Participants-
https://pages.razorpay.com/bandgapinr

International Participants-
https://pages.razorpay.com/bandgapdollar

All the best and happy learning
05:44:09
@telegram_984517860:tchncs.deKunal VSD (Telegram)bandgap_spec2layout.png
Download bandgap_spec2layout.png
05:44:08

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