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RISC-V is a free and open ISA. Part of #riscv:matrix.org. Bridged to Telegram: https://t.me/riscv. Unofficial.29 Servers

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1 Jun 2023
@CyReVolt:matrix.orgDaniel aka CyReVolt 🐢And I have already written a tool in Rust that does the Xmodem transfer, anyway. All that's needed is the receiving side for further transfers and some glue logic.10:46:28
@CyReVolt:matrix.orgDaniel aka CyReVolt 🐢On that note, the call for providing open tools for flashing is also on my list for later.10:47:26
@telegram_492445660:tchncs.dePierce Andjelkovic (Telegram)
In reply to @raitobezarius:matrix.org
It's bureaucry oriented development
Are you describing RISC-V or UEFI? 🤔
@raitobezarius:matrix.orgraitobezariusthey share this similarity :)11:29:30
@raitobezarius:matrix.orgraitobezariusI'd argue though that RISC V specs are more technical than bureaucratic11:29:40
@raitobezarius:matrix.orgraitobezariusBut UEFI…11:29:43
@telegram_492445660:tchncs.dePierce Andjelkovic (Telegram)
In reply to @raitobezarius:matrix.org
I'd argue though that RISC V specs are more technical than bureaucratic
You should bring up the topic of the thead vectors...
@raitobezarius:matrix.orgraitobezarius? (link)11:32:44
@raitobezarius:matrix.orgraitobezariusI'm not following RISC V specifications work as much as before11:32:59
@telegram_420423942:tchncs.defs (Telegram) changed their display name from Fabiano Silos (Telegram) to fs (Telegram).12:57:40
@telegram_6039465207:tchncs.dechayan约瑟 (Telegram) joined the room.15:29:22
@CyReVolt:matrix.orgDaniel aka CyReVolt 🐢
In reply to @CyReVolt:matrix.org

That is what the hyperscalers do with LinuxBoot.
Google, Meta, ByteDance etc use it to speed up their infra's boot processes, gain easier customizability and get rid of attack surface.

We also use it together with oreboot, and you can put it on top of U-Boot SPL + SBI on RISC-V.

I'll be giving a talk later today, a RISC-V Tech Session, where I elaborate on bootloaders and solution options. A demo will be part of it.

slides are here, recoding will be published soonish, something within the next 24, said Rafael from RISC-V

Hi there.

I would like to ask you about the correct way to get an instruction length somewhere in hypervisor/kernel.
I have the following code:

#define GET_INSN_LENGTH(insn)                               \
    (((insn) & INSN_LENGTH_MASK) == INSN_LENGTH_32 ? 4 : 2) \

uint32_t read_instr(unsigned long pc)
    uint16_t instr16 = *(uint16_t *)pc;

    if ( GET_INSN_LENGTH(instr16) == 2 )
       return (uint32_t)instr16;
       return *(uint32_t *)pc;

The code above doesn't look safe as it requires double-read ( so instruction can be changed during this reads ).

Another one question how hardware is supposed to deal with this situation. Can it indeed fetch in 16-bit quantities?
It looks like it is the smallest possible amount of bit in case when we have compressed ISA.

My guess was that it reads a i-cache size amount of bits and then pipeline tracks whether an insturction is 16 or 32 bit
but still doesn't clear what h/w does in case an instruction span i-cacheline boundary?

@telegram_597360262:tchncs.deSandy ⟁⃤ (Telegram) changed their display name from Sandeep Kumar (Telegram) to Sandy ⟁⃤ (Telegram).17:51:20
@telegram_597360262:tchncs.deSandy ⟁⃤ (Telegram) set a profile picture.17:51:37

from the RISCV ISA doc:

1.2 Instruction Length Encoding
The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit
boundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensions
with variable-length instructions, where each instruction can be any number of 16-bit instruction
parcels in length and parcels are naturally aligned on 16-bit boundaries. The standard compressed
ISA extension described in Chapter 12 reduces code size by providing compressed 16-bit instructions
and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on
any 16-bit boundary to improve code density

but does it mean that h/w will always fetch 16-bit, then check length of an instruction and etc?

@telegram_1046396226:tchncs.deSergey Brutyan (Telegram) joined the room.20:37:26
@telegram_1833752090:tchncs.dematt (Telegram)how many types of ribbon cables (including connectors) for tiny LCD screens there are?21:39:35
@CyReVolt:matrix.orgDaniel aka CyReVolt 🐢Tons. You need to be really careful. If power supplies are on other pins than expected... 🔥22:03:47
@telegram_1833752090:tchncs.dematt (Telegram)can you see if there are any power components constructed on the pins? I need to analyze some pins to see if I can attach 'em on an external motherboard.22:34:41
@telegram_1833752090:tchncs.dematt (Telegram)* can you see if there are any power components constructed on the pins? I need to analyze some pins to see if I can attach 'em on an external tiny motherboard.22:35:21
2 Jun 2023
@CyReVolt:matrix.orgDaniel aka CyReVolt 🐢 Hard to say without schematics etc - you can measure with a multimeter on the board, given small enough probes, and identify ground on the display side. If you manage to disassemble it in the right spots, take a photo and post it, someone here might be able to help.
That's far off topic though.
@telegram_1833752090:tchncs.dematt (Telegram)ok09:25:23
@telegram_1225117510:tchncs.de꧁༺ÐëαÐshot༻꧂ (Telegram)Hey, I'm trying to implement dynamic branch controlling unit for pipelined risc-v architecture processor. Is there any resources to catch up my work easily?12:51:44
@telegram_1094718443:tchncs.deAnatolii (Telegram) New RISC-V MCU CH32X035 has Programmable Protocol I/O Controller. It's small core like PIO in RP2040 MCU. 12:55:07
3 Jun 2023
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