| 30 Mar 2021 |
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| Budavarapu Mahesh | HI | 16:37:22 |
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| 31 Mar 2021 |
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 mehdi | In reply to@_slack_skywater-pdk_U01662JEWBH:matrix.org
Hi everyone! mehdi and I have been working on OpenFASOC a fully open source analog block generation based on FASOC (https://github.com/idea-fasoc/fasoc) using fully open-source tools like OpenROAD, Magic and Netgen. So far, we have pushed an automated temperature sensor generator to github: https://github.com/idea-fasoc/OpenFASOC. Please have a look and try our generator and let us know if there are any issues. We would be happy to assist. Thanks! Hi! We have updated our spice simulation flow and added a partial + full verification modes. We have done so because of the slow runtime of ngspice. I would be really grateful if people could help us improve it. Any inputs or PRs are welcome! https://github.com/idea-fasoc/OpenFASOC
Our channel: #skywater-pdk_fasoc:matrix.org | 11:57:55 |
 Olof Kindgren | Hi mehdi OpenFASOC is very interesting. I haven't had the opportunity to work with analog flows yet but people seems to be excited about it | 13:36:46 |
| mehdi | Hi Olof Kindgren -- Great to hear that! It would be really cool to hear what could be improved in my flow (I am trying to set a CI right now). | 13:40:18 |
| Olof Kindgren | mehdi FuseSoC integration would be nice of course 🙂 | 13:40:41 |
| mehdi | Olof Kindgren I will check it! I am curious how it could be used for OpenFASOC.. | 13:53:56 |
| Olof Kindgren | mehdi My thinking is that people can build a design with FuseSoC where part of it can be generated by OpenFASOC through the FuseSoC generator API | 14:09:37 |
| Olof Kindgren | FuseSoC currently has a bunch of generators for turning high-level descriptions into something that the EDA tools natively understand | 14:10:23 |
| Olof Kindgren | Example of this would be generating a wishbone or AXI interconnect from a memory map, generating verilog from Chisel, generating $readmemh hex files from C code etc | 14:12:04 |
| Olof Kindgren | I know too little yet about the analog flow to see exactly where we can do the integration, but Klas Nordmark and I are adding support for the OpenLane flow in Edalize, which is the backend used by FuseSoC. So I think it will become clearer down the road. It would be good to already now look at how OpenFASOC can be used in conjunction with this | 14:13:38 |
 Klas Nordmark | Yeah, I mean generating and adding analog/mixed signal blocks that aren't built straight from RTL would be part of what we minimally need for a full chip flow anyway, for IO if nothing else | 14:17:02 |
| mehdi | Olof Kindgren This sounds great! We do something similar with Socrates to stitch together our SoC (core + using APB/AHB peripherals). The issue is Socrates is an ARM tool (not open source). My understanding is FuseSoC could be used in a similar way? | 14:17:28 |
| Olof Kindgren | mehdi I haven't used Socrates but from what I understand it does a bit more than what FuseSoC does. We can say it like this, FuseSoC contains all the parts needed to build a socrates tool | 14:20:48 |
