| 5 Sep 2024 |
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 Adrien | Hi Guys, I've hit an issue with yosys techmap for Xilinx :
/usr/bin/../share/yosys/xilinx/cells_map.v:151: ERROR: Signal \A' with invalid width range -1!` | 09:32:14 |
| Adrien | * Hi Guys, I've hit an issue with yosys techmap for Xilinx :
/usr/bin/../share/yosys/xilinx/cells_map.v:151: ERROR: Signal '\\A' with invalid width range -1!\ | 09:32:32 |
| Adrien | I'm not sure this originates from my design or if it's a Yosys issue.
Is there a specific message to look for in Yosys log to get a candidate hint ? | 09:34:43 |
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| Adrien | Next issue : Yosys plainly rejects designs that use task $fatal
(actually these occurrences are generated from ghdl from conversions of asserts)
Shouldn't these be just ignored instead ? | 14:30:16 |
| Adrien | Yosys error message is : ERROR: Can't resolve task name '$fatal' | 14:31:51 |
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| @libera_Guest42:catircservices.org | Hi, I have some problems about the sat pass in yosys | 03:01:17 |
