| 6 Sep 2024 |
 @libera_Guest42:catircservices.org | Does sat support set two signal not equal? For example there are two registers : reg [3:0] a, a1; how can I constraint a != a1? | 03:03:17 |
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 mewt | 10;rgb:9700/9d00/b40011;rgb:2000/2700/460025 | 03:28:56 |
| mewt | sorry | 03:29:02 |
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| hm | Hi everyone, I asked a question about using the 'sat' pass in Yosys for parsing Verilog files a couple of hours ago. I would really appreciate it if anyone with experience could offer some guidance. Thanks in advance for your help! | 08:12:49 |
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