In reply to @jackkoenig-57e1805540f3a6eec0665030:gitter.im
Let me preface by saying that I am not an expert here and might be wrong, but I do support designers building high-performance stuff in modern technologies and I'm pretty sure they don't use tri-state at all.
You are right that the mux trees would be massive (this can be mitigated a bit as most ASIC technologies provide Mux4 primitives which help a little, although that's more with routing than with area), and the tri-state logic would certainly have fewer wires which helps with routing, but I think you run into drive strength issues with the length of the wire (those tri-state gates have to get pretty big), and the length of time it takes to drive the wire may be just too limiting on your clock speed to make the benefits worth it

I'm trying to generate vcd file in recent version of Chisel. I used to use

test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation))

to generate vcd file. However, recent version of chisel test use "svsim" so i tried

simulate(new MyModule).withAnnotations(Seq(WriteVcdAnnotation))

to generate vcd file. It dose not work well. Which keywords should i use to generate vcd files? Thanks.

In reply to @jooyeon111-60d94deb6da03739847fd235:gitter.im

I'm trying to generate vcd file in recent version of Chisel. I used to use

test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation))

to generate vcd file. However, recent version of chisel test use "svsim" so i tried

simulate(new MyModule).withAnnotations(Seq(WriteVcdAnnotation))

to generate vcd file. It dose not work well. Which keywords should i use to generate vcd files? Thanks.

I've been working on a simulator that will generate not only Vcd files for chiselsim like chiseltest but also a waveform viewer suited for chisel. However it's currently under development.

I realized a demo which contains 2 simulators ParametricSimulator and another one to generate waves for chisel types: https://github.com/rameloni/tywaves-chisel-demo

The parametric simulator is fully working and you can use it to generate Vcd. But it relies on the development branch of chisel. In my readme it should be clear enough how to use it.

I was going to create a post later today about my project. I've already talked with the CIRCT group (especially Fabian) about that but I haven't published the demo yet.

It's a demo and it has limited support for specific chisel waveforms but as I said ParametricSimulator should be enough for you at the moment

I am getting some confusing results in a family of operations. I have a Vec(batchSize, UInt(64.W)) and want to perform element operations on two of these vecs.
The following code produces incorrect results:

workingSpace := (io.in1, io.in2).zipped.map(_ <= _)
// workingSpace result is (0x1, 0x31, 0x0)

Am I missing something about the way a mapped binary operator over a vector works?

I am getting some confusing results in a family of operations. I have a Vec(batchSize, UInt(64.W)) and want to perform element operations on two of these vecs.
The following code produces incorrect results:

workingSpace := (io.in1, io.in2).zipped.map(_ <= _)
// workingSpace result is (0x1, 0x31, 0x0)
// Result should be (true, false, true)

Am I missing something about the way a mapped binary operator over a vector works?