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Chisel Lang

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Discussion about the Chisel Hardware Description Language. Use the following Scastie Template for testing and questions: https://bit.ly/3u3zr0e.3 Servers

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15 Apr 2021
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) Since your I/O interface of your memory is very different depending on whether it is maskable, I would highly recommend making two separate classes. 18:03:50
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) If you are going to make the interface to the outside world the same, then I would think that having the maskable parameter makes sense. 18:04:23
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) Essentially, the rule I would follow is: If people can use your module with the same code, no matter what the parameter choice is, then make it one class. If the outside code will also be different, splitting it up might be a good idea. 18:05:13
@jackkoenig:matrix.orgJack Koenig
In reply to @ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.im
This was my attempt, but it does not work: https://scastie.scala-lang.org/6TXAgPNnQJqm2EOwRv9jSw
It doesn't work because you didn't provide the necessary evidence πŸ™‚ I don't think I'd recommend this but here's something that works: https://scastie.scala-lang.org/jackkoenig/dTgYm8qRTpWSon1pWAyjsw/27
18:43:59
@jackkoenig:matrix.orgJack Koenig
In reply to @jackkoenig:matrix.org
It doesn't work because you didn't provide the necessary evidence πŸ™‚ I don't think I'd recommend this but here's something that works: https://scastie.scala-lang.org/jackkoenig/dTgYm8qRTpWSon1pWAyjsw/27
implicit val ev: T <:< chisel3.Vec[_] = null

This is πŸ§‘β€πŸ³πŸ’‹

18:45:17
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) Guys, how about creating a factory object whose apply method determines which of the two modules to generate (maskable or non-maskable)? In this way the user would get a single interface to talk to while at the backend we would have two separate memory modules like Kevin told. 19:12:33
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan)
  1. why did you make rdData and wrData an Option? Seems like they are always available.
I thought using the if in bundle would mean to always enclose the data inside an Option
19:14:02
@jackkoenig:matrix.orgJack Koenig
In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
Guys, how about creating a factory object whose apply method determines which of the two modules to generate (maskable or non-maskable)? In this way the user would get a single interface to talk to while at the backend we would have two separate memory modules like Kevin told.
That seems reasonable to me, but I do think that Kevin's point still stands. The user code for dealing with the maskable vs. non-maskable is going to look very different (it similarly will have to deal with Vec vs. UInt) so it's worth considering what it looks like for the user.
19:14:51
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) Yes, for maskable the user has to send a different bundle with Vec as inputs vs sending just UInt for non-maskable. 19:19:03
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) figuring out 😟 19:22:24
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) I guess for now I would create two separate classes for the user. Either they want a block ram that supports maskable writes or they want a block ram that doesn't. 19:30:59
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) * I guess for now I would create two separate classes for the user. Either they want a block ram that supports maskable writes or they want a block ram that doesn't. 19:31:41
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) Btw @jackkoenig what is the difference b/w creating a ROM with VecInit or with SyncReadMem that has no write port and just a loadMemoryFromFile construct. Are there any differences in terms of the FIRRTL emitted and later porting on the FPGA or taking to the ASIC? 19:36:16
@jackkoenig:matrix.orgJack Koenig
In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
Btw @jackkoenig what is the difference b/w creating a ROM with VecInit or with SyncReadMem that has no write port and just a loadMemoryFromFile construct. Are there any differences in terms of the FIRRTL emitted and later porting on the FPGA or taking to the ASIC?
VecInit is much uglier Verilog but is synthesizable for ASICs. AFAIK, no ASIC synthesis tool will accept memory loading
19:36:56
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) What does it make for an FPGA? A distributed LUT ram maybe 19:41:36
@jackkoenig:matrix.orgJack Koenig
In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
What does it make for an FPGA? A distributed LUT ram maybe
Probably LUT rams but I'm not sure
19:42:22
@hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.imhadirkhan10 (Muhammad Hadir Khan) Okay, thanks. 19:42:56
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) Jack, have you ever tried running an initialized read only memory through DC or similar? If the synthesis tools don't like it, we could implement a special emission strategy where we detect that a memory only has read ports and the turn it into a switch statement or whatever the tools like. 19:55:15
@jackkoenig:matrix.orgJack Koenig
In reply to @ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.im
Jack, have you ever tried running an initialized read only memory through DC or similar? If the synthesis tools don't like it, we could implement a special emission strategy where we detect that a memory only has read ports and the turn it into a switch statement or whatever the tools like.
Nope, certainly worth checking if they support $readmemh now (they certainly didn't in the past). read ports only or not I think it's worth doing some pattern matching and emitting switch statements, just a question of dev time πŸ™‚
19:56:22
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) Yeah, time ... 20:20:58
@ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.imekiwi (Kevin Laeufer) I guess in general I am just a proponent of using Mem for ROMs since it provides more structural information to the firrtl compiler. But yeah, the current emission strategy is probably not so great for ASIC tools 20:21:44
17 Apr 2021
@banality-5e79fa47d73408ce4fddd3fe:gitter.imbanality (banality) joined the room.07:02:11
@banality-5e79fa47d73408ce4fddd3fe:gitter.imbanality (banality) Hello, Is there, Nowadays, a good way of creating an array of Modules that can be dynamically indexed by hardware signal? 07:02:12
@quarky93:matrix.orgQuarky93 (Tong Wu)
val modules = VecInit(Seq.fill(8) { Module(new MyModule).io })

you can have a Vec of IO bundles

07:16:04
@quarky93:matrix.orgQuarky93 (Tong Wu)it's not ideal but that's the way i've been doing it07:16:31
@banality-5e79fa47d73408ce4fddd3fe:gitter.imbanality (banality) @quarky93:matrix.org OK, thank you. 07:24:05
@quarky93:matrix.orgQuarky93 (Tong Wu) I guess you could also put the modules themselves in an array and then put their ios in another Vec which is hardware indexable 07:26:11
@quarky93:matrix.orgQuarky93 (Tong Wu)That way you don’t lose the module objects themselves in case you need some field information in them07:26:57
@quarky93:matrix.orgQuarky93 (Tong Wu)A computed latency field perhaps07:27:27
@banality-5e79fa47d73408ce4fddd3fe:gitter.imbanality (banality) Thanks, I know that 07:37:09

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