Muhammad Hadir Khan (Gitter): That example is a bit sparse... I've used the following to try to show RRArbiter (a round robin arbiter) before:

/** Define a "packet" data type */
class Packet extends Bundle {
  val addr = UInt(32.W)
  val data = UInt(64.W)
}

/** Instantiate 4 input queues, 1 arbiter, 1 output queue */
val inQ  = Seq.fill(4)(Module(new Queue(new Packet, 4)))
val arb  = Module(new RRArbiter(new Packet, 4))
val outQ = Module(new Queue(new Packet, 16))

/** Wire everything up */
(arb.io.in).zip(inQ).foreach{ case (a, b) => a <> b.io.deq }
outQ.io.enq <> arb.io.out

not comprehensive
Definitely true
and does not show how one might actually connect their modules (producers and consumers) with this Arbiter module
Is that not what the example does? Sure it's simple but it has 2 producers and 1 consumer

/** Define a "packet" data type */
class Packet extends Bundle {
  val addr = UInt(32.W)
  val data = UInt(64.W)
}

/** Instantiate 4 input queues, 1 arbiter, 1 output queue */
val inQ  = Seq.fill(4)(Module(new Queue(new Packet, 4)))
val arb  = Module(new RRArbiter(new Packet, 4))
val outQ = Module(new Queue(new Packet, 16))

/** Wire everything up */
(arb.io.in).zip(inQ).foreach{ case (a, b) => a <> b.io.deq }
outQ.io.enq <> arb.io.out

```class DataSPadTester(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig {
val io = IO(new Bundle{
val dataIn = Decoupled(SInt(dataWidth.W))
...
})
protected val testCommonPad: CommonSPad = Module(new CommonSPad(padSize, dataWidth))
protected val testCommonPadIO = testCommonPad.io
testCommonPadIO.dataPath.writeInData.valid := io.dataIn.valid
testCommonPadIO.dataPath.writeInData.bits := io.dataIn.bits
io.dataIn.ready := testCommonPadIO.dataPath.writeInData.ready // error
io.dataIn.ready := true.B // it also prompted error
...
}
class CommonSPad(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig{
lazy val io: SPadModuleIOTest = IO(new SPadModuleIOTest(dataWidth = dataWidth, padSize = padSize))
protected val decoupledDataIO: DecoupledIO[SInt] = io.dataPath.writeInData
protected val dataWire: SInt = Wire(SInt(dataWidth.W))
protected val padWriteIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W))
protected val padReadIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W))
protected val commonDataSPad: SyncReadMem[SInt] = SyncReadMem(padSize, SInt(dataWidth.W))

decoupledDataIO.ready := true.B
...
}