In reply to @ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.im
This was my attempt, but it does not work: https://scastie.scala-lang.org/6TXAgPNnQJqm2EOwRv9jSw

In reply to @jackkoenig:matrix.org
It doesn't work because you didn't provide the necessary evidence 🙂 I don't think I'd recommend this but here's something that works: https://scastie.scala-lang.org/jackkoenig/dTgYm8qRTpWSon1pWAyjsw/27

implicit val ev: T <:< chisel3.Vec[_] = null

This is 🧑‍🍳💋

1. why did you make rdData and wrData an Option? Seems like they are always available.

In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
Guys, how about creating a factory object whose apply method determines which of the two modules to generate (maskable or non-maskable)? In this way the user would get a single interface to talk to while at the backend we would have two separate memory modules like Kevin told.

In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
Btw @jackkoenig what is the difference b/w creating a ROM with VecInit or with SyncReadMem that has no write port and just a loadMemoryFromFile construct. Are there any differences in terms of the FIRRTL emitted and later porting on the FPGA or taking to the ASIC?

In reply to @hadirkhan10-5e33aa61d73408ce4fd844f8:gitter.im
What does it make for an FPGA? A distributed LUT ram maybe

In reply to @ekiwi-5eb8a5fdd73408ce4fe34c5b:gitter.im
Jack, have you ever tried running an initialized read only memory through DC or similar? If the synthesis tools don't like it, we could implement a special emission strategy where we detect that a memory only has read ports and the turn it into a switch statement or whatever the tools like.

val modules = VecInit(Seq.fill(8) { Module(new MyModule).io })

you can have a Vec of IO bundles