 | Chisel Lang | 116 Members |
| Discussion about the Chisel Hardware Description Language. Use the following Scastie Template for testing and questions: https://bit.ly/33esRsD | 2 Servers |
| Chisel Lang | 116 Members |
| Discussion about the Chisel Hardware Description Language. Use the following Scastie Template for testing and questions: https://bit.ly/33esRsD | 2 Servers |
| Sender | Message | Time |
|---|---|---|
| 13 Jan 2021 | ||
 ekiwi (Gitter) | Feel free to open a PR (either adding a parameter or with a new Queue class as you initially suggested) against the chisel3 repo: https://github.com/chipsalliance/chisel3 | 17:18:05 |
| 14 Jan 2021 | ||
 Ken Zhang (Gitter) | (edited) Any idea? @jackkoenig => Hi all, I have the exact same question as in this SO thread -> https://stackoverflow.com/questions/60772192/how-do-i-make-an-individual-rocket-tile-asynchronous-to-the-rest-of-the-system Basically I have a multi-core system, I would like to put the tiles async to the rest of the system, the answer used to work, but after upgrading to the new rocket-chip HoB (https://github.com/chipsalliance/rocket-chip), this is broken, I got elaboration error with the following configurations: ``` class WithAsynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) // Default FreedomEConfig class DefaultFreedomEConfig extends Config ( new WithNBreakpoints(2) ++ new WithNExtTopInterrupts(0) ++ new WithJtagDTM ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(128) ++ new WithDefaultBtb ++ new WithAsynchronousRocketTiles++ new TinyConfig ) ``` My diplomacy knowledge is not up to date, I got: ``` [error] java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph: [error] The following node has 2 outward bindings connected to it, but 1 sources were specified to the node constructor. [error] Either the number of outward := bindings should be exactly equal to the number of sources, or connect this node on the right-hand side of a :=* [error] source dummyClockGroupSourceNode.node node: [error] parents: dummyClockGroupSourceNode/sys [error] locator: (ClockGroup.scala:79:81) [error] [error] 0 inward nodes bound: [] [error] 1 outward nodes bound: [query-sys.clock_sources] [error] [error] number of known := bindings to inward nodes: 0 [error] number of known := bindings to outward nodes: 2 [error] number of binding queries from inward nodes: 0 [error] number of binding queries from outward nodes: 0 [error] 1 outward parameters: [ClockGroupSourceParameters()] [error] [error] [error] ... [error] at freechips.rocketchip.diplomacy.SourceNode.resolveStar(Nodes.scala:1612) [error] at freechips.rocketchip.diplomacy.MixedNode.liftedTree1$1(Nodes.scala:1057) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27$lzycompute(Nodes.scala:1028) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping$lzycompute(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iDirectPorts$1(Nodes.scala:1105) [error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245) [error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242) [error] at scala.collection.immutable.List.flatMap(List.scala:355) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts$lzycompute(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.EphemeralNode.oForward(Nodes.scala:1508) [error] at freechips.rocketchip.diplomacy.MixedNode.iTrace(Nodes.scala:1120) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iPorts$1(Nodes.scala:1143) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.iPorts$lzycompute(Nodes.scala:1143) [error] at freechips.rocketchip.diplomacy.MixedNod ``` | 05:54:35 |
 Jack Koenig (Gitter) | This one is beyond my knowledge, have you looked at what the Chipyard folks are doing with Async crossings? | 05:54:35 |
| Ken Zhang (Gitter) | (edited) ... freechips.rocketchip.diplomacy.MixedNod ``` => ... freechips.rocketchip.diplomacy.MixedNod ``` | 05:54:53 |
| Jack Koenig (Gitter) | I haven't, just wondering if they might have code you could base yours on | 05:54:53 |
 Vladimir Milovanović (Gitter) | (edited) ... contribute it. => ... contribute it. | 11:42:04 |
 Guy Hutchison (Gitter) | Also, to answer the original question, in ASICs small* memories are inefficient and so are normally implemented in discrete flops, and a SyncReadMem implementation will likely end up having some additional logic (such as an output holding register) that increases its area. Nonetheless +1 for providing a SyncReadMem based Queue implementation. *No consensus on what "small" is, but in previous projects any memory less than 8-16 entries deep was implemented with flops. | 11:42:04 |
| Ken Zhang (Gitter) | (edited) ... freechips.rocketchip.diplomacy.MixedNod ``` => ... freechips.rocketchip.diplomacy.MixedNod ``` | 12:13:20 |
| Ken Zhang (Gitter) | Thanks Jack! Yeah diplomacy is always tricky... I did look at the chipyad repo but I couldn't find any example of async crossing of the tiles, I did find though that the use of | 12:13:20 |
| Ken Zhang (Gitter) | (edited) Thanks Jack! Yeah diplomacy is always tricky... I did look at the chipyad repo but I couldn't find any example of async crossing of the tiles, I did find though that the use of `case TilesLocated(InSubsystem)`? https://github.com/ucb-bar/chipyard/blob/dev/generators/chipyard/src/main/scala/ConfigFragments.scala#L60 => Hi all, I have the exact same question as in this SO thread -> https://stackoverflow.com/questions/60772192/how-do-i-make-an-individual-rocket-tile-asynchronous-to-the-rest-of-the-system Basically I have a multi-core system, I would like to put the tiles async to the rest of the system, the answer used to work, but after upgrading to the new rocket-chip HoB (https://github.com/chipsalliance/rocket-chip), this is broken, I got elaboration error with the following configurations: ``` class WithAsynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) // Default FreedomEConfig class DefaultFreedomEConfig extends Config ( new WithNBreakpoints(2) ++ new WithNExtTopInterrupts(0) ++ new WithJtagDTM ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(128) ++ new WithDefaultBtb ++ new WithAsynchronousRocketTiles++ new TinyConfig ) ``` My diplomacy knowledge is not up to date, I got: ``` [error] java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph: [error] The following node has 2 outward bindings connected to it, but 1 sources were specified to the node constructor. [error] Either the number of outward := bindings should be exactly equal to the number of sources, or connect this node on the right-hand side of a :=* [error] source dummyClockGroupSourceNode.node node: [error] parents: dummyClockGroupSourceNode/sys [error] locator: (ClockGroup.scala:79:81) [error] [error] 0 inward nodes bound: [] [error] 1 outward nodes bound: [query-sys.clock_sources] [error] [error] number of known := bindings to inward nodes: 0 [error] number of known := bindings to outward nodes: 2 [error] number of binding queries from inward nodes: 0 [error] number of binding queries from outward nodes: 0 [error] 1 outward parameters: [ClockGroupSourceParameters()] [error] [error] [error] ... [error] at freechips.rocketchip.diplomacy.SourceNode.resolveStar(Nodes.scala:1612) [error] at freechips.rocketchip.diplomacy.MixedNode.liftedTree1$1(Nodes.scala:1057) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27$lzycompute(Nodes.scala:1028) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping$lzycompute(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iDirectPorts$1(Nodes.scala:1105) [error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245) [error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242) [error] at scala.collection.immutable.List.flatMap(List.scala:355) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts$lzycompute(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.EphemeralNode.oForward(Nodes.scala:1508) [error] at freechips.rocketchip.diplomacy.MixedNode.iTrace(Nodes.scala:1120) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iPorts$1(Nodes.scala:1143) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.iPorts$lzycompute(Nodes.scala:1143) [error] at freechips.rocketchip.diplomacy.MixedNod ``` | 12:15:10 |
| Ken Zhang (Gitter) | Is there anyone/anywhere else I can look for an example of tile async crossing? I am aware that the whole interface between tile and the interconnect is being largely re-written/re-factored, so it would be good to have an example of the new API. | 12:15:10 |
| Vladimir Milovanović (Gitter) | (edited) ... contribute it. => ... contribute it. | 12:44:05 |
| Vladimir Milovanović (Gitter) | Thank you both on your answers. We'll try to implement it by adding a parameter (taking care to preserve backward compatibility) and open a PR when we finish. Sure, for anything small , using SRAMs would be inefficient since it implies a huge overhead logic (in addressing above all), but I was thinking more of depths >64 where the overhead is easily amortized by the way smaller bit-cells. | 12:44:06 |
| Ken Zhang (Gitter) | (edited) Is there anyone/anywhere else I can look for an example of tile async crossing? I am aware that the whole interface between tile and the interconnect is being largely re-written/re-factored, so it would be good to have an example of the new API. => Hi all, I have the exact same question as in this SO thread -> https://stackoverflow.com/questions/60772192/how-do-i-make-an-individual-rocket-tile-asynchronous-to-the-rest-of-the-system Basically I have a multi-core system, I would like to put the tiles async to the rest of the system, the answer used to work, but after upgrading to the new rocket-chip HoB (https://github.com/chipsalliance/rocket-chip), this is broken, I got elaboration error with the following configurations: ``` class WithAsynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) // Default FreedomEConfig class DefaultFreedomEConfig extends Config ( new WithNBreakpoints(2) ++ new WithNExtTopInterrupts(0) ++ new WithJtagDTM ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(128) ++ new WithDefaultBtb ++ new WithAsynchronousRocketTiles++ new TinyConfig ) ``` My diplomacy knowledge is not up to date, I got: ``` [error] java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph: [error] The following node has 2 outward bindings connected to it, but 1 sources were specified to the node constructor. [error] Either the number of outward := bindings should be exactly equal to the number of sources, or connect this node on the right-hand side of a :=* [error] source dummyClockGroupSourceNode.node node: [error] parents: dummyClockGroupSourceNode/sys [error] locator: (ClockGroup.scala:79:81) [error] [error] 0 inward nodes bound: [] [error] 1 outward nodes bound: [query-sys.clock_sources] [error] [error] number of known := bindings to inward nodes: 0 [error] number of known := bindings to outward nodes: 2 [error] number of binding queries from inward nodes: 0 [error] number of binding queries from outward nodes: 0 [error] 1 outward parameters: [ClockGroupSourceParameters()] [error] [error] [error] ... [error] at freechips.rocketchip.diplomacy.SourceNode.resolveStar(Nodes.scala:1612) [error] at freechips.rocketchip.diplomacy.MixedNode.liftedTree1$1(Nodes.scala:1057) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27$lzycompute(Nodes.scala:1028) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping$lzycompute(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iDirectPorts$1(Nodes.scala:1105) [error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245) [error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242) [error] at scala.collection.immutable.List.flatMap(List.scala:355) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts$lzycompute(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.EphemeralNode.oForward(Nodes.scala:1508) [error] at freechips.rocketchip.diplomacy.MixedNode.iTrace(Nodes.scala:1120) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iPorts$1(Nodes.scala:1143) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.iPorts$lzycompute(Nodes.scala:1143) [error] at freechips.rocketchip.diplomacy.MixedNod ``` | 20:48:52 |
| Jack Koenig (Gitter) | Chipyard is the only place I know of, maybe try searching Github but I bet Chipyard is ahead of what anyone else is doing in the open-source | 20:48:52 |
| Ken Zhang (Gitter) | (edited) ... freechips.rocketchip.diplomacy.MixedNod ``` => ... freechips.rocketchip.diplomacy.MixedNod ``` | 21:31:55 |
| ekiwi (Gitter) | the chipyard mailing list might also be a good place to ask about this | 21:31:55 |
| Ken Zhang (Gitter) | (edited) ... freechips.rocketchip.diplomacy.MixedNod ``` => ... freechips.rocketchip.diplomacy.MixedNod ``` | 22:42:00 |
| Ken Zhang (Gitter) | Thanks Jack and Kevin! Could you point me to the mailing list? How could I subscribe and join the list? | 22:42:00 |
| Ken Zhang (Gitter) | (edited) Thanks Jack and Kevin! Could you point me to the mailing list? How could I subscribe and join the list? => Hi all, I have the exact same question as in this SO thread -> https://stackoverflow.com/questions/60772192/how-do-i-make-an-individual-rocket-tile-asynchronous-to-the-rest-of-the-system Basically I have a multi-core system, I would like to put the tiles async to the rest of the system, the answer used to work, but after upgrading to the new rocket-chip HoB (https://github.com/chipsalliance/rocket-chip), this is broken, I got elaboration error with the following configurations: ``` class WithAsynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) // Default FreedomEConfig class DefaultFreedomEConfig extends Config ( new WithNBreakpoints(2) ++ new WithNExtTopInterrupts(0) ++ new WithJtagDTM ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(128) ++ new WithDefaultBtb ++ new WithAsynchronousRocketTiles++ new TinyConfig ) ``` My diplomacy knowledge is not up to date, I got: ``` [error] java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph: [error] The following node has 2 outward bindings connected to it, but 1 sources were specified to the node constructor. [error] Either the number of outward := bindings should be exactly equal to the number of sources, or connect this node on the right-hand side of a :=* [error] source dummyClockGroupSourceNode.node node: [error] parents: dummyClockGroupSourceNode/sys [error] locator: (ClockGroup.scala:79:81) [error] [error] 0 inward nodes bound: [] [error] 1 outward nodes bound: [query-sys.clock_sources] [error] [error] number of known := bindings to inward nodes: 0 [error] number of known := bindings to outward nodes: 2 [error] number of binding queries from inward nodes: 0 [error] number of binding queries from outward nodes: 0 [error] 1 outward parameters: [ClockGroupSourceParameters()] [error] [error] [error] ... [error] at freechips.rocketchip.diplomacy.SourceNode.resolveStar(Nodes.scala:1612) [error] at freechips.rocketchip.diplomacy.MixedNode.liftedTree1$1(Nodes.scala:1057) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27$lzycompute(Nodes.scala:1028) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping$lzycompute(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iDirectPorts$1(Nodes.scala:1105) [error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245) [error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242) [error] at scala.collection.immutable.List.flatMap(List.scala:355) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts$lzycompute(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.EphemeralNode.oForward(Nodes.scala:1508) [error] at freechips.rocketchip.diplomacy.MixedNode.iTrace(Nodes.scala:1120) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iPorts$1(Nodes.scala:1143) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.iPorts$lzycompute(Nodes.scala:1143) [error] at freechips.rocketchip.diplomacy.MixedNod ``` | 22:55:35 |
| Jack Koenig (Gitter) | Here's the GoogleGroup, https://groups.google.com/g/chipyard, you can also join by sending an email to chipyard-subscribe@googlegroups.com | 22:55:35 |
| Ken Zhang (Gitter) | Excellent, thanks for the prompt response Jack! Much appreciated! | 23:04:39 |
| Ken Zhang (Gitter) | (edited) Excellent, thanks for the prompt response Jack! Much appreciated! => Hi all, I have the exact same question as in this SO thread -> https://stackoverflow.com/questions/60772192/how-do-i-make-an-individual-rocket-tile-asynchronous-to-the-rest-of-the-system Basically I have a multi-core system, I would like to put the tiles async to the rest of the system, the answer used to work, but after upgrading to the new rocket-chip HoB (https://github.com/chipsalliance/rocket-chip), this is broken, I got elaboration error with the following configurations: ``` class WithAsynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( crossingType = AsynchronousCrossing() )) case other => other } }) // Default FreedomEConfig class DefaultFreedomEConfig extends Config ( new WithNBreakpoints(2) ++ new WithNExtTopInterrupts(0) ++ new WithJtagDTM ++ new WithL1ICacheWays(2) ++ new WithL1ICacheSets(128) ++ new WithDefaultBtb ++ new WithAsynchronousRocketTiles++ new TinyConfig ) ``` My diplomacy knowledge is not up to date, I got: ``` [error] java.lang.IllegalArgumentException: requirement failed: Diplomacy has detected a problem with your graph: [error] The following node has 2 outward bindings connected to it, but 1 sources were specified to the node constructor. [error] Either the number of outward := bindings should be exactly equal to the number of sources, or connect this node on the right-hand side of a :=* [error] source dummyClockGroupSourceNode.node node: [error] parents: dummyClockGroupSourceNode/sys [error] locator: (ClockGroup.scala:79:81) [error] [error] 0 inward nodes bound: [] [error] 1 outward nodes bound: [query-sys.clock_sources] [error] [error] number of known := bindings to inward nodes: 0 [error] number of known := bindings to outward nodes: 2 [error] number of binding queries from inward nodes: 0 [error] number of binding queries from outward nodes: 0 [error] 1 outward parameters: [ClockGroupSourceParameters()] [error] [error] [error] ... [error] at freechips.rocketchip.diplomacy.SourceNode.resolveStar(Nodes.scala:1612) [error] at freechips.rocketchip.diplomacy.MixedNode.liftedTree1$1(Nodes.scala:1057) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27$lzycompute(Nodes.scala:1028) [error] at freechips.rocketchip.diplomacy.MixedNode.x$27(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping$lzycompute(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.oPortMapping(Nodes.scala:1027) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iDirectPorts$1(Nodes.scala:1105) [error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245) [error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242) [error] at scala.collection.immutable.List.flatMap(List.scala:355) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts$lzycompute(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.MixedNode.iDirectPorts(Nodes.scala:1103) [error] at freechips.rocketchip.diplomacy.EphemeralNode.oForward(Nodes.scala:1508) [error] at freechips.rocketchip.diplomacy.MixedNode.iTrace(Nodes.scala:1120) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$iPorts$1(Nodes.scala:1143) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.iPorts$lzycompute(Nodes.scala:1143) [error] at freechips.rocketchip.diplomacy.MixedNod ``` | 23:04:40 |
| 15 Jan 2021 | ||
 k8z (Gitter) | Hi, I am trying to change the top level circuit name of my design under test by passing the--top-name option in iotesters.Driver.execute, however no name change seems to occur (the output verilog file and the verilator command generated still use the original circuit name). I also tried using the --output-file option, but that doesn't seem to work either...Does anyone know how can I change top name using options passed to iotesters.Driver.execute? Here is my example: https://scastie.scala-lang.org/k8z/AKNlBXZfRn6INcUowrK7LQ/41 | 01:40:36 |
| Jack Koenig (Gitter) | top-name isn't really intended for setting the name of the top (although I can see why one would think that), it's more of a workaround for a historic limitation that no longer exists. To change the name of your top module, you need to set it in the module itself: https://www.chisel-lang.org/chisel3/docs/explanations/naming.html#set-a-module-name | 01:53:47 |
| k8z (Gitter) | Ok, that worked, thanks! | 02:09:14 |
| 16 Jan 2021 | ||
 Vadzim Dambrouski (Gitter) joined the room. | 15:05:50 | |
| Vadzim Dambrouski (Gitter) | Hello. Can you please tell me what is the best way to fix clone type error in this small example? https://scastie.scala-lang.org/T36fAc1ARqeEBP2ZlSkwNQ | 15:05:51 |
| Vadzim Dambrouski (Gitter) | Do I need to create a new class for my Bundle? | 15:06:07 |
| 20 Jan 2021 | ||
 gitter-badger (The Gitter Badger) joined the room. | 06:43:56 | |