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Chisel Lang

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Discussion about the Chisel Hardware Description Language. Use the following Scastie Template for testing and questions: https://bit.ly/3eP6hue1 Servers

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Timestamp Message
21 May 2020
01:51:29@gitter_claford-v-lawrence:matrix.orgclaford-v-lawrence (Gitter) @kojung Just FYI, io testers can also use flat spec and everything.
03:58:46@gitter_kojung:matrix.orgJung Ko (Gitter) joined the room.
03:58:48@gitter_kojung:matrix.orgJung Ko (Gitter) My simplified unit test looks like this:
import org.scalatest._
import chisel3._
import chiseltest._
import chiseltest.experimental.TestOptionBuilder._
import chiseltest.internal.VerilatorBackendAnnotation

class FooTest extends FlatSpec with ChiselScalatestTester with Matchers {
    val annos = Seq(VerilatorBackendAnnotation)
    "Foo" should "work" in {
        test(new Foo()).withAnnotations(annos) { dut =>
            ... some tests ...
        }
    }
}
03:59:01@gitter_kojung:matrix.orgJung Ko (Gitter) and I'm just calling the test inside sbt with testOnly FooTest. Looks like testOnly doesn't like the --tr-verbose flag.
04:04:02@gitter_kojung:matrix.orgJung Ko (Gitter) I'm hoping to see the same detail as I would get if I used iotester and passed --is-verbose. Essentially I would like to see the peek/poke values as time progresses. Thanks for your help. Could you point me to the file + line that I need to change? If that works, I'd be happy to submit an issue and all the necessary details.
04:04:09@gitter_kojung:matrix.orgJung Ko (Gitter) Oh... let me try the treadle.VerboseAnnotation.
04:04:32@gitter_kojung:matrix.orgJung Ko (Gitter) Oh, WOW.. treadle.VerboseAnnotation is super verbose.... It printed out the states of all internal wires! :-)
04:04:38@gitter_kojung:matrix.orgJung Ko (Gitter) OK, it's better than nothing. Thank you for your help. If you can point me to the fix for verilator, I can submit an issue.
04:05:01@gitter_kojung:matrix.orgJung Ko (Gitter)OK, will do. Thanks!
05:32:37@gitterbot:matrix.orgGitter Integration joined the room.
05:45:45@gitter_kojung:matrix.orgJung Ko (Gitter) Hi everyone. I'm new to Chisel and I'm stuck right now, wondering if someone here could help me. I've switched to using chiseltest because I really like the FlatSpec format. However, I can't find the equivalent of --is-verbose flag that exists in iotester framework. Does anyone know how I can turn the verbose flag on? Thanks a lot in advance!!
05:46:41@gitter_kojung:matrix.orgJung Ko (Gitter) @chick , I'm using the verilator backend.
08:36:40@gitter_hrishim_gitlab:matrix.orgHrishikesh (Gitter) @claford-v-lawrence thank you
09:26:40@gitter_claford-v-lawrence:matrix.orgclaford-v-lawrence (Gitter)No problem:)
17:29:08@gitter_kojung:matrix.orgJung Ko (Gitter) @claford-v-lawrence , that's interesting. I'm starting a brand new project with a lifetime of ~1 year. Do you recommend I stick to iotesters + flatspec or should I move to chiseltester in order to be future proof?
17:35:20@gitter_kojung:matrix.orgJung Ko (Gitter) @chick , I created ticket freechipsproject/chisel3#1447. I tried my best to capture the context, hopefully it's clear enough what feature I'm requesting.
18:23:58@gitter_kojung:matrix.orgJung Ko (Gitter) OK, I switched back to iotester but kept FlatSpec. Everything works fine now and the --is-verbose flag gives me just the right amount of debug information I need to debug my generator. Thanks @claford-v-lawrence for the suggestion, I appreciate it.
20:15:46@gitter_tampler:matrix.orgBoris V.Kuznetsov (Gitter) @kojung You may take a look at this project. It currently uses iotesters, but delivers a simpler integration and a higher performance test framework, than 'scalatest`
20:16:27@gitter_tampler:matrix.orgBoris V.Kuznetsov (Gitter) I'm working on another FIRRTL simulator and will be delivering soon
20:16:48@gitter_tampler:matrix.orgBoris V.Kuznetsov (Gitter) (edited) I'm working on another FIRRTL simulator and will be delivering soon => @kojung You may take a look at [this](https://github.com/chisel-crew/chisel-hello) project. It currently uses `iotesters`, but delivers a simpler integration and a higher performance test framework, than `scalatest`
22 May 2020
13:59:34@gitter_cousteaulecommandant:matrix.orgcousteau (Gitter) (edited) same for a clock enable that acts like a soft clock gate (but not an actual clock gate). CE is like the third most common and important input signal, after clock and reset, so I see how that could be useful => Well, depending on whether you want a 2D vector of bits, UInts, or something that works both as 2D vector of bits and 1D vector of wide UInts
13:59:34@gitter_hrishim_gitlab:matrix.orgHrishikesh (Gitter)Thank you. Thats what I ended up doing - 2D vector of bits
24 May 2020
15:48:51@gitter_claford-v-lawrence:matrix.orgclaford-v-lawrence (Gitter) @kojung Sorry for the delay in response
15:53:08@gitter_claford-v-lawrence:matrix.orgclaford-v-lawrence (Gitter) Yes, I would recommend (chisel-testers2)[https://github.com/ucb-bar/chisel-testers2]. This is more powerful than iotesters, and I’m currently migrating some of my tests from iotesters to chiseltest
15:53:41@gitter_claford-v-lawrence:matrix.orgclaford-v-lawrence (Gitter)Oops, my markdown syntax has gone a little rusty
26 May 2020
02:19:48@gitter_hafred:matrix.orgFrederick HONG (Gitter) joined the room.
02:19:49@gitter_hafred:matrix.orgFrederick HONG (Gitter) Could someone kindly elaborate on these? I have been wondering how chisel3.stage.emitVerilog (https://github.com/freechipsproject/chisel3/blob/646bf95a84cc48dc13854c254b4d1511821dd8dd/src/main/scala/chisel3/stage/ChiselStage.scala#L98) works actually, how does it manage to emit the Verilog?
02:21:24@gitter_hafred:matrix.orgFrederick HONG (Gitter) And how does it include those ifdefdefine RANDOMIZE for the
02:23:05@gitter_hafred:matrix.orgFrederick HONG (Gitter)test harness? How do we manually utilize these testing snippets without in a simple sbt environment?
12:59:40@gitter_juliusbaxter:matrix.orgJulius Baxter (Gitter)

Bit of a rocket-chip specific question here, but I'm keen to try and access the raw interrupt inputs to a tile (mainly to route to a clock gate control).
I've tried adding the following to BaseTileModuleImp in BaseTile.scala:

  val ints = IO(Bool(OUTPUT))
  val ints_flat = outer.intXbar.intnode.in.map { case (i, e) => i.orR }
  ints := ints_flat.orR

Please forgive the hackiest Chisel in the world, I don't even know if that's the correct way of extracting and or-reducing the interrupt input vector from a sequence of tuples, but that doesn't work because, first of all, intXbar is protected inside the abstract class:

  protected val intXbar = LazyModule(new IntXbar)

and then if I juggle things around and remove the protected and put the ints_flat in the abstract class, it blows up with:

[error] Caused by: java.lang.IllegalArgumentException: requirement failed: intXbar.intnode.in should only be called from the context of its module implementation

In fact, most things I try end with that one.

I think diplomacy is in the way here - all I really want is to be able to pick off all of the raw interrupt lines. Anyone got any suggestions?


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