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Chisel Lang

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Discussion about the Chisel Hardware Description Language. Use the following Scastie Template for testing and questions: https://bit.ly/33esRsD1 Servers

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11 Aug 2020
@gitter_hadirkhan10:matrix.orgMuhammad Hadir Khan (Gitter) (edited) ... and understand the ... => ... and comprehend the ... 08:02:54
@seldridge:matrix.orgSchuyler Eldridge

Muhammad Hadir Khan (Gitter): That example is a bit sparse... I've used the following to try to show RRArbiter (a round robin arbiter) before:

/** Define a "packet" data type */
class Packet extends Bundle {
  val addr = UInt(32.W)
  val data = UInt(64.W)
}

/** Instantiate 4 input queues, 1 arbiter, 1 output queue */
val inQ  = Seq.fill(4)(Module(new Queue(new Packet, 4)))
val arb  = Module(new RRArbiter(new Packet, 4))
val outQ = Module(new Queue(new Packet, 16))

/** Wire everything up */
(arb.io.in).zip(inQ).foreach{ case (a, b) => a <> b.io.deq }
outQ.io.enq <> arb.io.out

16:53:30
@seldridge:matrix.orgSchuyler Eldridge This is 4 queues sequenced into 1 queue using a round robin arbiter. The underlying data type is Packet. 16:54:11
@seldridge:matrix.orgSchuyler Eldridge Arbiters and queues use a decoupled interface which includes ready, valid, and bits lines. Here, the arbiter and all the queues have that same interface and you can just wire them up with <>. 16:56:47
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter)
not comprehensive
Definitely true
and does not show how one might actually connect their modules (producers and consumers) with this Arbiter module
Is that not what the example does? Sure it's simple but it has 2 producers and 1 consumer
19:19:23
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) (edited) ... comprehensive Definitely true > and does not show how one might actually connect their modules (producers and consumers) with this Arbiter module Is ... => ... comprehensive Definitely true > and does not show how one might actually connect their modules (producers and consumers) with this Arbiter module Is ... 19:19:26
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter)In any case, I am digging for some more uses which could help you19:19:38
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) Here's an example, that is not that different from the example, although connects all producers at the same time: https://github.com/chipsalliance/rocket-chip/blob/d71c5a674275676b9c870a20cb0a42cd039a4115/src/main/scala/rocket/PTW.scala#L105 19:22:01
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) Ah @hadirkhan10 I just realized we're in basically opposite time zones so this is a bit tricky, but I'm happy to help explain examples. While concise and lacking explanation, the use case in the ScalaDoc that you linked is actually more-or-less how it's used, I'll turn it into a Scastie example so you can run the code in the browser to see what the output looks like a tweak it and use it to ask more questions 19:25:19
@gitter_seldridge:matrix.orgSchuyler Eldridge (Gitter) Ack... it looks like the Matrix bridge broke (again). @hadirkhan10: here's an example I've used in presentations before: 19:26:42
@gitter_seldridge:matrix.orgSchuyler Eldridge (Gitter)
/** Define a "packet" data type */
class Packet extends Bundle {
  val addr = UInt(32.W)
  val data = UInt(64.W)
}

/** Instantiate 4 input queues, 1 arbiter, 1 output queue */
val inQ  = Seq.fill(4)(Module(new Queue(new Packet, 4)))
val arb  = Module(new RRArbiter(new Packet, 4))
val outQ = Module(new Queue(new Packet, 16))

/** Wire everything up */
(arb.io.in).zip(inQ).foreach{ case (a, b) => a <> b.io.deq }
outQ.io.enq <> arb.io.out
19:26:56
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) Ah nice, thanks @seldridge! And here's a Scastie example you can run in your browser and inspect the Verilog. I just took the example from the ScalaDoc and turned it into something that would build Verilog: https://scastie.scala-lang.org/piPH1waOSJCAZI6l6zRRdQ 19:28:10
@gitter_seldridge:matrix.orgSchuyler Eldridge (Gitter):100:19:28:39
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) My module Foo, is just wrapping up the Arbiter so is really just connecting things, but you can see how the connections turn out. Important thing to keep in mind is that the producer and consumer interfaces are read-valid interfaces (called Decoupled in Chisel) 19:29:02
12 Aug 2020
@gitter_hafred:matrix.orgFrederick Hong (Gitter) changed their display name from Frederick HONG (Gitter) to Frederick Hong (Gitter).01:42:12
@gitter_hafred:matrix.orgFrederick Hong (Gitter) Hi, I was trying to initiate a DecoupledIO type, but it showed the Sink is unwriteable by current module. I am confused that why is it unwriteable here? 01:42:14
@gitter_hafred:matrix.orgFrederick Hong (Gitter)

```class DataSPadTester(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig {
val io = IO(new Bundle{
val dataIn = Decoupled(SInt(dataWidth.W))
...
})
protected val testCommonPad: CommonSPad = Module(new CommonSPad(padSize, dataWidth))
protected val testCommonPadIO = testCommonPad.io
testCommonPadIO.dataPath.writeInData.valid := io.dataIn.valid
testCommonPadIO.dataPath.writeInData.bits := io.dataIn.bits
io.dataIn.ready := testCommonPadIO.dataPath.writeInData.ready // error
io.dataIn.ready := true.B // it also prompted error
...
}
class CommonSPad(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig{
lazy val io: SPadModuleIOTest = IO(new SPadModuleIOTest(dataWidth = dataWidth, padSize = padSize))
protected val decoupledDataIO: DecoupledIO[SInt] = io.dataPath.writeInData
protected val dataWire: SInt = Wire(SInt(dataWidth.W))
protected val padWriteIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W))
protected val padReadIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W))
protected val commonDataSPad: SyncReadMem[SInt] = SyncReadMem(padSize, SInt(dataWidth.W))

decoupledDataIO.ready := true.B
...
}

01:42:25
@gitter_hafred:matrix.orgFrederick Hong (Gitter) (edited) ... ... } => ... ... }``` 01:42:38
@gitter_hafred:matrix.orgFrederick Hong (Gitter) (edited) ```class DataSPadTester(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig { val io = IO(new Bundle{ val dataIn = Decoupled(SInt(dataWidth.W)) ... }) protected val testCommonPad: CommonSPad = Module(new CommonSPad(padSize, dataWidth)) protected val testCommonPadIO = testCommonPad.io testCommonPadIO.dataPath.writeInData.valid := io.dataIn.valid testCommonPadIO.dataPath.writeInData.bits := io.dataIn.bits io.dataIn.ready := testCommonPadIO.dataPath.writeInData.ready // error io.dataIn.ready := true.B // it also prompted error ... } class CommonSPad(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig{ lazy val io: SPadModuleIOTest = IO(new SPadModuleIOTest(dataWidth = dataWidth, padSize = padSize)) protected val decoupledDataIO: DecoupledIO[SInt] = io.dataPath.writeInData protected val dataWire: SInt = Wire(SInt(dataWidth.W)) protected val padWriteIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W)) protected val padReadIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W)) protected val commonDataSPad: SyncReadMem[SInt] = SyncReadMem(padSize, SInt(dataWidth.W)) decoupledDataIO.ready := true.B ... }``` => ``` class DataSPadTester(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig { val io = IO(new Bundle{ val dataIn = Decoupled(SInt(dataWidth.W)) ... }) protected val testCommonPad: CommonSPad = Module(new CommonSPad(padSize, dataWidth)) protected val testCommonPadIO = testCommonPad.io testCommonPadIO.dataPath.writeInData.valid := io.dataIn.valid testCommonPadIO.dataPath.writeInData.bits := io.dataIn.bits io.dataIn.ready := testCommonPadIO.dataPath.writeInData.ready // error io.dataIn.ready := true.B // it also prompted error ... } class CommonSPad(padSize: Int, dataWidth: Int) extends Module with BPGDSizeConfig{ lazy val io: SPadModuleIOTest = IO(new SPadModuleIOTest(dataWidth = dataWidth, padSize = padSize)) protected val decoupledDataIO: DecoupledIO[SInt] = io.dataPath.writeInData protected val dataWire: SInt = Wire(SInt(dataWidth.W)) protected val padWriteIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W)) protected val padReadIndexReg: UInt = RegInit(0.U(log2Ceil(padSize).W)) protected val commonDataSPad: SyncReadMem[SInt] = SyncReadMem(padSize, SInt(dataWidth.W)) decoupledDataIO.ready := true.B ... } ``` 01:43:01
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) io.dataIn.ready is an Input 01:43:56
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) the default directions for Decoupled are that bits and valid are Output, ready in an Input 01:44:22
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) you can flip all of those with Flipped(...) 01:44:30
@gitter_hafred:matrix.orgFrederick Hong (Gitter) The weird thing is that if I only instantiate the child module CommonSPad, the decoupledDataIO.ready := true.B can be elaborated without error in the chisel-tester2 01:51:27
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) That seems unrelated though right? In DataSPadTester you instantiate CommonSPad earlier than the lines that error so it seems like decoupledDataIO.ready := true.B works there as well 01:53:20
@gitter_baltazarortiz:matrix.orgBaltazar Ortiz (Gitter) Hey all, probably another silly error on my part, but I am trying to set up an AddressSet starting at 0x8000_0000 and getting requirement failed: AddressSet negative base is ambiguous: -2147483648. I'm currently trying AddressSet(BigInt(0x80000000), 0xffff) but have also tried dropping the BigInt or even just putting in 2147483648 as the BigInt value and they all fail with this or similar errors. 03:25:05
@gitter_baltazarortiz:matrix.orgBaltazar Ortiz (Gitter) Is there a way to make an AddressSet operate on higher addresses like this? I'm trying to use a TLFilter to segment up some memory. 03:25:47
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter)This is because Int literals are 32-bit signed in Scala/Java04:03:09
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) you can append an L, eg. 0x8000_0000L for a 64-bit signed Long, or go via Strings to BigInt 04:03:36
@gitter_jackkoenig:matrix.orgJack Koenig (Gitter) BigInt("80000000", 16) (the 16 for base-16 as you can probably guess) 04:03:57
@gitter_baltazarortiz:matrix.orgBaltazar Ortiz (Gitter) thanks! I'll give this a shot in the morning 04:04:09

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