| 22 Mar 2021 |
|  @townndisrentia1976:matrix.org left the room. | 14:47:17 |
|  Harris banned @townndisrentia1976:matrix.org (spamming). | 16:00:53 |
 _slack_skywater-pdk_U016ELL4X4M | [efabless/openlane] Issue closed by agorararmard | 17:10:31 |
| 23 Mar 2021 |
 Anton Blanchard | Ahmed Ghazy Amr Gouhar FYI I fixed the issue where tracks (usually metal 5) get created in outer space. I hit it on the first shuttle: https://github.com/The-OpenROAD-Project/OpenROAD/pull/602 | 00:28:42 |
| Anton Blanchard | In reply to@_slack_skywater-pdk_U01FYLU6TKP:matrix.org
Ahmed Ghazy Amr Gouhar FYI I fixed the issue where tracks (usually metal 5) get created in outer space. I hit it on the first shuttle: https://github.com/The-OpenROAD-Project/OpenROAD/pull/602 Fix just went upstream | 00:29:18 |
| 24 Mar 2021 |
 Philipp Gühring | I forgot to add the link: https://github.com/lnis-uofu/LSOracle | 00:30:47 |
 matt venn | I'm looking at the latest openlane v0.9 and develop of caravel. Aim is to build user project wrapper with the default user project | 10:40:12 |
| matt venn | 
Download image.png | 10:40:47 |
| matt venn | I have to update the makefile to prevent use of rc6: | 10:40:47 |
| matt venn | Then I run make user_project_wrapper from the openlane directory inside caravel | 10:41:04 |
| matt venn | After about 10 minutes of printed warnings like this: | 10:41:14 |
| matt venn | [WARNING PSM-0030] Vsrc location at (-1399901.776um, -1914116.416um) and size =10.000um, is not located on a power stripe. Moving to closest stripe at (0.000um, 10.880um) | 10:41:28 |
| matt venn | It finally fails with this message: | 10:41:34 |
| matt venn | 
Download image.png | 10:41:49 |
| matt venn | Is anyone else testing the latest openlane + caravel? Again, this is current develop on caravel and v0.9 openlane | 10:42:16 |
 Wajeh ul hasan | 
Download image.png | 11:04:05 |
| Wajeh ul hasan | Amr Gouhar Ahmed Ghazy
I was running the flow on OpenLane v0.9, the powered netlist excludes the wires declared for some reason. | 11:04:05 |
 Amr Gouhar | In reply to@_slack_skywater-pdk_U016Y9FMA2Y:matrix.org
Amr Gouhar Ahmed Ghazy
I was running the flow on OpenLane v0.9, the powered netlist excludes the wires declared for some reason. Wajeh ul hasan: They are time expensive to write and not needed in most cases. You can re-enable it with https://github.com/efabless/openlane/blob/6ac4378a138810cd6f8de34b33cb01b04ce9b0bd/configuration/general.tcl#L22. | 13:15:08 |
| Amr Gouhar | In reply to@_slack_skywater-pdk_U01634FSETZ:matrix.org
Wajeh ul hasan: They are time expensive to write and not needed in most cases. You can re-enable it with https://github.com/efabless/openlane/blob/6ac4378a138810cd6f8de34b33cb01b04ce9b0bd/configuration/general.tcl#L22. Setting a default nettype as wire in the beginning of the file would be a more efficient solution tho if you're trying to simulate. | 13:16:03 |
| Wajeh ul hasan | In reply to@_slack_skywater-pdk_U01634FSETZ:matrix.org
Setting a default nettype as wire in the beginning of the file would be a more efficient solution tho if you're trying to simulate. Thanks | 13:22:19 |
|  Boris Murmann joined the room. | 18:00:00 |
| 26 Mar 2021 |
|  hamza shabbir joined the room. | 19:13:10 |
| hamza shabbir changed their profile picture. | 19:13:12 |
| 28 Mar 2021 |
 Varun Majji | can anyone tell me what is the use of tlef files which always get merged with the lef files of standard cells and form merged lef in openlane | 06:57:36 |
 Lofty | I'm assuming the "t" is "template" | 07:32:14 |
| Lofty | Ah, "technology library exchange format" | 07:32:51 |
| 29 Mar 2021 |
|  Steven Huang changed their display name from StevenHuang to Steven Huang. | 16:35:08 |
| 30 Mar 2021 |
| matt venn | In reply to@_slack_skywater-pdk_U0172QZ342D:matrix.org
should have searched before asking - oops I wrote this up here: https://www.zerotoasiccourse.com/terminology/antenna-report/ | 11:08:40 |
|  Klas Nordmark joined the room. | 11:45:57 |
| Klas Nordmark | Hopefully not bringing up an old question here, but something that strikes me when reading the the docs is how there is a singular CLOCK_PERIOD and CLOCK_NET/PORT variable. Are designs with multiple clocks not supported? | 11:51:35 |
