| 3 Apr 2021 |
|  Ammar Kurd set a profile picture. | 10:00:03 |
 nvijayamanohar | In reply to@_slack_skywater-pdk_U016PTY0C2E:matrix.org
I ran into this issue a while back and the only fix I could find was to switch to a different simulation mode or to try to patch the cells manually ok, thanks Anish | 10:39:08 |
|  Slack Integration invited  _slack_skywater-pdk_U01TL6TT5H7. | 13:28:57 |
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 Tim Edwards | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
ok, thanks Anish nvijayamanohar: This was an error in the scripts used to prepare the verilog files from source. iverilog does not understand the "specify" sections in the files. Unfortunately, we discovered that some of the "specify" section includes buffers that split a net and generate a delayed signal. The scripts did not catch those, and so did not modify the net names to prevent disconnected signals. The "proper" solution is to leave in the specify sections, and to have iverilog do at least the minimum necessary parsing to connect the nets, even if it does not know how to handle the delays (I don't know if anyone has tested whether iverilog already does this or not. It was generating fatal errors on some of the "specify" section syntax, so we elected to remove the whole section). The trivial workaround for the whole problem is to define FUNCTIONAL in the testbench verilog (or in the call to iverilog; e.g., "iverilog -DFUNCTIONAL") to force it to use the functional, and not the behavioral, models. | 14:11:05 |
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| nvijayamanohar | In reply to@_slack_skywater-pdk_U016EM8L91B:matrix.org
nvijayamanohar: This was an error in the scripts used to prepare the verilog files from source. iverilog does not understand the "specify" sections in the files. Unfortunately, we discovered that some of the "specify" section includes buffers that split a net and generate a delayed signal. The scripts did not catch those, and so did not modify the net names to prevent disconnected signals. The "proper" solution is to leave in the specify sections, and to have iverilog do at least the minimum necessary parsing to connect the nets, even if it does not know how to handle the delays (I don't know if anyone has tested whether iverilog already does this or not. It was generating fatal errors on some of the "specify" section syntax, so we elected to remove the whole section). The trivial workaround for the whole problem is to define FUNCTIONAL in the testbench verilog (or in the call to iverilog; e.g., "iverilog -DFUNCTIONAL") to force it to use the functional, and not the behavioral, models. Hi Tim , | 19:33:47 |
| nvijayamanohar | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
Hi Tim , Thanks a lot for quick reply | 19:33:54 |
| nvijayamanohar | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
Thanks a lot for quick reply Facing the following error when i am using iverilog -DFUNCTIONAL | 19:34:23 |
 Anish | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
Facing the following error when i am using iverilog -DFUNCTIONAL you may need to define UNIT_DELAY (iirc as #1) | 19:35:33 |
| Anish | In reply to@_slack_skywater-pdk_U016PTY0C2E:matrix.org
you may need to define UNIT_DELAY (iirc as #1) here's an example for how to run iverilog with a gate-level netlist | 19:36:19 |
| Anish | In reply to@_slack_skywater-pdk_U016PTY0C2E:matrix.org
here's an example for how to run iverilog with a gate-level netlist https://github.com/asinghani/sky130-chip-vis/blob/main/examples/spm/run-sim.sh | 19:36:20 |
| nvijayamanohar | In reply to@_slack_skywater-pdk_U016PTY0C2E:matrix.org
https://github.com/asinghani/sky130-chip-vis/blob/main/examples/spm/run-sim.sh Hi Tim / Anish ,
Also , want one more help . Have you tried to use yosys . I am facing issues with yosys for inferring latches. ie if i have latches in my RTL (proper latches not inferred latches ) , the synthesis is identifying them as latches but it is not inserting a lib cell for latch. DO you have any clue / workaround for this ? | 19:37:05 |
| nvijayamanohar | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
Hi Tim / Anish ,
Also , want one more help . Have you tried to use yosys . I am facing issues with yosys for inferring latches. ie if i have latches in my RTL (proper latches not inferred latches ) , the synthesis is identifying them as latches but it is not inserting a lib cell for latch. DO you have any clue / workaround for this ? Thanks a lot Anish | 19:53:40 |
 Russell Friesenhahn | In reply to@_slack_skywater-pdk_U01SSFX4PEK:matrix.org
Thanks a lot Anish Is openlane the right place for @n | 19:54:03 |
| Russell Friesenhahn | In reply toundefined
(edited) ... for @n => ... for nvijayamanohar to file this? Is it already fixed? Should it go in the PDK or standard cell repo? I ask because as the slack channel limits to the last 10000 messages, these kinds of discussions are invaluable in future IMO | 19:55:04 |
| Tim Edwards | In reply to@_slack_skywater-pdk_U018F616ZTL:matrix.org
Is openlane the right place for nvijayamanohar to file this? Is it already fixed? Should it go in the PDK or standard cell repo? I ask because as the slack channel limits to the last 10000 messages, these kinds of discussions are invaluable in future IMO Russell Friesenhahn: There are tools that can skim the contents of a slack workspace so that an archive web page can be made from it. We definitely need to do something like that. We already have important information in messages that have disappeared off the top of the discussions. | 20:37:33 |
| Tim Edwards | In reply to@_slack_skywater-pdk_U016EM8L91B:matrix.org
Russell Friesenhahn: There are tools that can skim the contents of a slack workspace so that an archive web page can be made from it. We definitely need to do something like that. We already have important information in messages that have disappeared off the top of the discussions. nvijayamanohar: The latch mapping has been done in openlane; the verilog modules that create the mapping are part of the open_pdks distribution. Also mux mapping, full adder mapping, and tristate buffer mapping. | 20:39:39 |
| 4 Apr 2021 |
| nvijayamanohar | In reply to@_slack_skywater-pdk_U016EM8L91B:matrix.org
nvijayamanohar: The latch mapping has been done in openlane; the verilog modules that create the mapping are part of the open_pdks distribution. Also mux mapping, full adder mapping, and tristate buffer mapping. Thanks everyone for valuable feedback and quick help | 02:00:42 |
| 5 Apr 2021 |
| Slack Integration invited  Bhawandeep Singh Harsh. | 05:13:43 |
| Bhawandeep Singh Harsh joined the room. | 05:13:43 |
| Bhawandeep Singh Harsh changed their display name from _slack_skywater-pdk_U01T99NG9FD to Bhawandeep Singh Harsh. | 05:14:28 |
| Bhawandeep Singh Harsh set a profile picture. | 05:14:29 |
| Slack Integration invited  RAHUL GUPTA. | 05:43:48 |
| RAHUL GUPTA joined the room. | 05:43:49 |
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