yes; so I have a new transform added (which basically adds parity generation and checkers for all registers in design), after this the DCE is run; and it removes one of the nodes that is generated from a register portion (whos output cone is optimized by DCE), and it does not remove the use of that signal from its output cone.

example:

input data[15:0]
output out
output out1 --> not used optimized
output error_or

out = xor data[7:0]
out1 = xor data[15:8] --> dce
check_1 = and data[15:8] --> dce
check_0 = and data[7:0]

error_or = check_0 or check_1

so; the final output after DCE looks like this:

input data[15:0]
output out
output error_or

out = xor data[7:0]
check_0 = and data[7:0]

error_or = check_0 or check_1

Chisel (the actual Scala program) can only emit .fir. We've intentionally avoided trying to have Chisel emit .fir.mlir because that is pretty unstable and would cause Chisel to need to be closely coupled to both MLIR (which could change something about the .mlir serialization) or CIRCT (which could change how it chooses to represent things).

You can do this with firtool directly via firtool -parse-only to get the .fir.mlir right after firtool reads it (convert .fir to ..mlir), firtool -ir-fir to get .mlir after the FIRRTL portion of the firtool pipeline, firtool -ir-hw to get .mlir after the HW portion of the firtool pipeline, firtool -ir-sv to get .mlir after HW constructs have been converted to SV, and firtool -ir-verilog to get the .mlir that is used for Verilog emission (after names are cleaned up, wires are spilled, etc.). Without specifying any of these options you get .sv.

circt.stage.ChiselStage has aliases for most of these with the --target option. --target chirrtl is .fir, --target firrtl is firtool -ir-fir, --target hw is firtool -ir-hw, and --target verilog or --target systemverilog are .v/.sv.

There's currently no option to dump at multiple points unless you use some of the lower level MLIR options like--mlir-print-ir-after=<pass>.

I think I worded my question wrong, sorry 😅

• Chisel emits FIRRTL spec 1.2.0
• firtool converts to the MLIR representation
• Is there any way convert MLIR to FIRRTL spec 2.1.0+?

I think I worded my question wrong, sorry 😅

• Chisel emits FIRRTL spec 1.2.0
• firtool converts to the MLIR representation
• Is there any way convert MLIR to the corresponding FIRRTL spec 2.1.0+? (I didn't see an option in firtool to do this)

I think I worded my question wrong, sorry 😅

• Chisel emits FIRRTL spec 1.2.0
• firtool converts to the MLIR representation
• Is there any way convert MLIR to the newer FIRRTL 2.1.0 spec form? (I didn't see an option in firtool to do this)

Thanks!