In reply to @jurevreca12-6012b66fd73408ce4ff9fd3c:gitter.im
No. I just felt like this should be able to work, but I wasn't sure, since I saw that now there are some .fir.mlir files and https://www.chisel-lang.org/docs/appendix/versioning this table doesn't specify this as ok.

That table should be updated or include something about firtool versions. That table is really talking about what version of different Scala projects works together. We've tried pretty hard to make firtool parse almost anything it's given FIRRTL-wise. Also, .lo.fir if a very restricted subset of FIRRTL produces by the Scala-based FIRRTL Compiler (SFC), so I would not expect there to be a problem with that.

The only known problem is that firtool never supported fixed point or interval types. These were exceedingly rarely used, so, again, I wouldn't expect you to run into this. I also think .lo.fir removed these in the SFC.

Hey I was trying to write a simple FIRRTL annotation with the CustomFileEmission trait. However, I don't fully understand how it works, sometimes it prints out the file other times no.

Is there anyone that knows a good reference to write a custom annotation?

Moreover, I also tried to use existing annotations from here: https://circt.llvm.org/docs/Dialects/FIRRTL/FIRRTLAnnotations/ but it seems that those annotations are available for firrtl2 while the ChiselAnnotation class works with firrtl library.

CustomFileEmission is not supported with firtool/CIRCT (because trait inheritance is not represented when annotations are written to disk---this requires having a JVM to reflectively build the annotation and then query it's run time type information, i.e., this was always a bad idea). There is now support for custom annotations and passes in CIRCT with some additional setup.

Roughly, you can register your annotations using this function: https://github.com/llvm/circt/blob/2caafc76bb1f35a92868c2c77fed114f40b9ffd7/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h#L450

You can then inject passes using MLIR's pass plugin feature to consume the annotation during the FIRRTL pipeline.

A sparse example of setting up a project to do this is here: https://github.com/uenoku/firtool-standalone-plugin

In reply to @seldridge:matrix.org

CustomFileEmission is not supported with firtool/CIRCT (because trait inheritance is not represented when annotations are written to disk---this requires having a JVM to reflectively build the annotation and then query it's run time type information, i.e., this was always a bad idea). There is now support for custom annotations and passes in CIRCT with some additional setup.

Roughly, you can register your annotations using this function: https://github.com/llvm/circt/blob/2caafc76bb1f35a92868c2c77fed114f40b9ffd7/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h#L450

You can then inject passes using MLIR's pass plugin feature to consume the annotation during the FIRRTL pipeline.

A sparse example of setting up a project to do this is here: https://github.com/uenoku/firtool-standalone-plugin

Hello everyone, I want to study how the Chisel code is elaborated to verilog, I have seen that it is first elaborated into a chisel IR, then, through transforms and annotations, it is translated to firrtl IR (high and lowfirrtl) and finally compiled to verilog.

Is there any official documentation that explains some details about that?

In reply to @rameloni:gitter.im

Hello everyone, I want to study how the Chisel code is elaborated to verilog, I have seen that it is first elaborated into a chisel IR, then, through transforms and annotations, it is translated to firrtl IR (high and lowfirrtl) and finally compiled to verilog.

Is there any official documentation that explains some details about that?

Here is my reason for studying that: I am currently working on a project that requires systematically to map chisel circuit elements to firrtl and verilog signals. I have already seen that there are two annotations that store a chisel and firrtl circuit respectively, however they are not directly linked. I only saw that the Converter object provides functions to convert chisel IR to Firrtl IR but it is private.

In reply to @seldridge:matrix.org
You may want to look at `llvm/circt` and specifically the debug dialect. That is infrastructure for tracking mappings of the high level language to Verilog. There’s more information here: https://circt.llvm.org/docs/Dialects/Debug/