| 19 Apr 2024 |
 sneakernet | In reply to @libera_bomb:catircservices.org
sneakernet what do you _love_ about RUst, if I might to ask? the design of static analysis during compilation that could be proofable | 03:47:18 |
 Kevin Ly | I'm just trying to read analog data (from potentiometer) through the ADC of an STM32F303 (on the discovery board).
My minimum programming involves:
let rcc = unsafe { &*RCC::ptr() };
let adc = unsafe { &*ADC1::ptr() };
rcc.ahbenr.write(|w| w.adc12en().enabled());
adc.cr.write(|w| {
w.advregen().intermediate();
w.advregen().enabled();
w.aden().enabled()
});
// some other stuff
hprint!("{}\n", adc.isr.read().adrdy().is_ready()); // to check if adc is ready
When I run the print statement in a loop to check if the adc is ever ready for conversion, it always reads "false." Am I missing any step for setting up the ADC? I'm referring to the data sheet for the STM32F303 to see the startup sequence.
A related question: Given that there is a startup time for the ADC after writing to the advregen, how do I know that I allow sufficient time between successive writes to the advregen bits? | 03:50:31 |
| Kevin Ly | * I'm just trying to read analog data (from potentiometer) through the ADC of an STM32F303 (on the discovery board).
\n
My minimum programming involves:
let rcc = unsafe { &*RCC::ptr() };
let adc = unsafe { &*ADC1::ptr() };
rcc.ahbenr.write(|w| w.adc12en().enabled());
adc.cr.write(|w| {
w.advregen().intermediate();
w.advregen().enabled();
w.aden().enabled()
});
// some other stuff
hprint!("{}\n", adc.isr.read().adrdy().is_ready()); // to check if adc is ready
When I run the print statement in a loop to check if the adc is ever ready for conversion, it always reads "false." Am I missing any step for setting up the ADC? I'm referring to the data sheet for the STM32F303 to see the startup sequence.
A related question: Given that there is a startup time for the ADC after writing to the advregen, how do I know that I allow sufficient time between successive writes to the advregen bits? | 03:50:41 |
| Kevin Ly | * (Sorry, I don't know how to format this message with line breaks)
I'm just trying to read analog data (from potentiometer) through the ADC of an STM32F303 (on the discovery board).
My minimum programming involves:
let rcc = unsafe { &*RCC::ptr() };
let adc = unsafe { &*ADC1::ptr() };
rcc.ahbenr.write(|w| w.adc12en().enabled());
adc.cr.write(|w| {
w.advregen().intermediate();
w.advregen().enabled();
w.aden().enabled()
});
// some other stuff
hprint!("{}\n", adc.isr.read().adrdy().is_ready()); // to check if adc is ready
When I run the print statement in a loop to check if the adc is ever ready for conversion, it always reads "false." Am I missing any step for setting up the ADC? I'm referring to the data sheet for the STM32F303 to see the startup sequence.
A related question: Given that there is a startup time for the ADC after writing to the advregen, how do I know that I allow sufficient time between successive writes to the advregen bits? | 03:50:57 |
 bomb | sneakernet good answer :) | 03:52:55 |
| sneakernet | In reply to @kebonly:matrix.org
(Sorry, I don't know how to format this message with line breaks)
I'm just trying to read analog data (from potentiometer) through the ADC of an STM32F303 (on the discovery board).
My minimum programming involves:
let rcc = unsafe { &*RCC::ptr() };
let adc = unsafe { &*ADC1::ptr() };
rcc.ahbenr.write(|w| w.adc12en().enabled());
adc.cr.write(|w| {
w.advregen().intermediate();
w.advregen().enabled();
w.aden().enabled()
});
// some other stuff
hprint!("{}\n", adc.isr.read().adrdy().is_ready()); // to check if adc is ready
When I run the print statement in a loop to check if the adc is ever ready for conversion, it always reads "false." Am I missing any step for setting up the ADC? I'm referring to the data sheet for the STM32F303 to see the startup sequence.
A related question: Given that there is a startup time for the ADC after writing to the advregen, how do I know that I allow sufficient time between successive writes to the advregen bits? I expect that since you are updating the ADC each time, it doesn't have enough time to produce a result | 03:53:18 |
| sneakernet | In reply to @libera_bomb:catircservices.org
sneakernet good answer :) is Rust going to get there, or will the current insanity require a fork? | 03:55:33 |
| bomb | no idea, I'm very new to Rust | 03:56:32 |
| sneakernet | I'm always looking to prove my math via Sel4 standards to create yet another toolchain | 03:56:45 |
| sneakernet | @bomb wanna make one of these https://github.com/redengin/sneakernet | 03:58:19 |
| sneakernet | * I'm always looking to prove my math via Sel4 standards to create yet another toolchain /s | 03:58:53 |
| sneakernet | I created firmware for esp32 (c++) but wanted to increase ability to create nodes by leveraging Rust | 04:00:25 |
| bomb | you want to invent the Skynet!? | 04:00:40 |
| sneakernet | skynet is my real job | 04:00:56 |
| sneakernet | this is a better net of real people | 04:01:47 |
| sneakernet | does anyone use usenet anymore... that would be my next functionality (rather than just a distributed dropbox) | 04:03:09 |
| sneakernet | In reply to @libera_bomb:catircservices.org
you want to invent the Skynet!? you want to deploy some SneakerNet nodes? I'll send you ready to plugin nodes | 04:06:04 |
| sneakernet | In reply to @libera_bomb:catircservices.org
you want to invent the Skynet!? * you want to deploy some SneakerNet nodes? I'll send you ready to plugin nodes (PM me your mailing info) | 04:07:09 |
| bomb | no | 04:27:16 |
| bomb | I'm laser focused on BombNet at the moment | 04:27:35 |
| sneakernet | tell me about BombNet | 04:27:53 |
| bomb | I won't tell you, but you'll hear about it. | 04:28:11 |
| bomb | loud and clear | 04:28:23 |
| sneakernet | In reply to @libera_bomb:catircservices.org
I won't tell you, but you'll hear about it. why is this an embedded topic? | 04:30:37 |
| sneakernet | In reply to @sneakernet:matrix.org
why is this an embedded topic? anyway, I'm happy to support others that have a game-changing idea - and I'll sign an NDA to ensure that you get all the credit/royalties | 04:33:26 |
| sneakernet | I just want to make comp-sci math again | 04:34:31 |
| bomb | sneakernet this is why https://www.youtube.com/watch?v=AvQlCv4K37c | 04:47:53 |
| sneakernet | In reply to @libera_bomb:catircservices.org
sneakernet this is why https://www.youtube.com/watch?v=AvQlCv4K37c are you designing a np-hard trigger? | 05:06:46 |
|  daud joined the room. | 07:08:03 |
 Kaspar | In reply to @sneakernet:matrix.org
ouch, so much specialization needed - what drives the pac's to be patched? can't the target pac be decoupled per rust-embedded architeture? Actually the pacs don't need patching anymore - I'll PR dropping those lines now. | 07:57:54 |
